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公开(公告)号：US11818959B2
公开(公告)日：2023-11-14
申请号：US17379780
申请日：2021-07-19
Applicant: Applied Materials, Inc.
Inventor： Hsin-wei Tseng , Chando Park , Jaesoo Ahn , Lin Xue , Mahendra Pakala
Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.
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公开(公告)号：US11723283B2
公开(公告)日：2023-08-08
申请号：US16871779
申请日：2020-05-11
Applicant: Applied Materials, Inc.
Inventor： Minrui Yu , Wenhui Wang , Jaesoo Ahn , Jong Mun Kim , Sahil Patel , Lin Xue , Chando Park , Mahendra Pakala , Chentsau Chris Ying , Huixiong Dai , Christopher S. Ngai
CPC classification number: H10N50/10 , G01R33/095 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/85 , H10N52/01 , H10N52/80
Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.
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公开(公告)号：US11251364B2
公开(公告)日：2022-02-15
申请号：US16773232
申请日：2020-01-27
Applicant: Applied Materials, Inc.
Inventor： Lin Xue , Chi Hong Ching , Jaesoo Ahn , Mahendra Pakala , Rongjun Wang
IPC: H01L27/22 , H01L43/08 , G11C11/16 , G11C11/15 , H01L21/768 , H01L45/00 , H01L27/24 , G11B5/31 , G11B5/39
Abstract: Embodiments herein provide film stacks that include a buffer layer; a synthetic ferrimagnet (SyF) coupling layer; and a capping layer, wherein the capping layer comprises one or more layers, and wherein the capping layer, the buffer layer, the SyF coupling layer, or a combination thereof, is not fabricated from Ru.
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公开(公告)号：US11145808B2
公开(公告)日：2021-10-12
申请号：US16681351
申请日：2019-11-12
Applicant: Applied Materials, Inc.
Inventor： Jong Mun Kim , Minrui Yu , Chando Park , Mang-Mang Ling , Jaesoo Ahn , Chentsau Chris Ying , Srinivas D. Nemani , Mahendra Pakala , Ellie Y. Yieh
Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.
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公开(公告)号：US11374170B2
公开(公告)日：2022-06-28
申请号：US16141470
申请日：2018-09-25
Applicant: Applied Materials, Inc.
Inventor： Lin Xue , Jaesoo Ahn , Hsin-wei Tseng , Mahendra Pakala
Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.
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Patent Agency Ranking
公开(公告)号：US11245069B2
公开(公告)日：2022-02-08
申请号：US15199006
申请日：2016-06-30
Applicant: Applied Materials, Inc.
Inventor： Lin Xue , Jaesoo Ahn , Mahendra Pakala , Chi Hong Ching , Rongjun Wang
Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one embodiment, the method includes patterning a film stack having a tunneling barrier layer disposed between a magnetic reference layer and a magnetic storage layer disposed on a substrate to remove a portion of the film stack from the substrate until an upper surface of the substrate is exposed, forming a sidewall passivation layer on sidewalls of the patterned film stack and subsequently performing a thermal annealing process to the film stack.
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公开(公告)号：US11239086B2
公开(公告)日：2022-02-01
申请号：US16396226
申请日：2019-04-26
Applicant: Applied Materials, Inc.
Inventor： Hsin-wei Tseng , Mahendra Pakala , Lin Xue , Jaesoo Ahn , Sajjad Amin Hassan
IPC: H01L21/306 , H01L23/544 , H01L21/822 , G03F9/00
Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.
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公开(公告)号：US10157787B2
公开(公告)日：2018-12-18
申请号：US15384219
申请日：2016-12-19
Applicant: APPLIED MATERIALS, INC.
Inventor： Jin Hee Park , Tae Hong Ha , Sang-Hyeob Lee , Thomas Jongwan Kwon , Jaesoo Ahn , Xianmin Tang , Er-Xuan Ping , Sree Kesapragada
IPC: H01L21/768 , H01L21/285 , C23C16/48 , C23C16/455 , C23C16/04 , C23C16/16 , C23C16/18 , C23C16/56 , H01L21/67 , H01L23/532 , H01L27/11556 , H01L27/11582
Abstract: Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.
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公开(公告)号：US09564582B2
公开(公告)日：2017-02-07
申请号：US14201439
申请日：2014-03-07
Applicant: Applied Materials, Inc.
Inventor： Mahendra Pakala , Mihaela Balseanu , Jonathan Germain , Jaesoo Ahn , Lin Xue
CPC classification number: H01L43/12 , H01L27/222 , H01L43/08
Abstract: A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.
Abstract translation: 公开了一种用于制造MRAM位的方法，其包括在处理期间沉积保护隧道势垒层的间隔层。 沉积的间隔层防止在后续处理中形成的副产物再沉积在隧道势垒层上。 这种再沉积可能导致产品失效并降低了制造成品率。 该方法还包括防腐损坏处理条件，以防损坏MRAM位的层。 非腐蚀性处理条件可以包括不使用卤素等离子体的蚀刻。 本文公开的实施例使用简化处理的蚀刻 - 沉积蚀刻序列。
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公开(公告)号：US12201030B2
公开(公告)日：2025-01-14
申请号：US18231414
申请日：2023-08-08
Applicant: Applied Materials, Inc.
Inventor： Minrui Yu , Wenhui Wang , Jaesoo Ahn , Jong Mun Kim , Sahil Patel , Lin Xue , Chando Park , Mahendra Pakala , Chentsau Chris Ying , Huixiong Dai , Christopher S. Ngai
Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.
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