公开(公告)号：US11131022B2

公开(公告)日：2021-09-28

申请号：US16412696

申请日：2019-05-15

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: C23C16/455 ,  H01L21/02 ,  H01L21/67

Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.

公开(公告)号：US11054815B2

公开(公告)日：2021-07-06

申请号：US15457016

申请日：2017-03-13

Applicant: Applied Materials, Inc.

Inventor： Bradley D. Schulze ,  Suketu Arun Parikh ,  Jimmy Iskandar ,  Jigar Bhadriklal Patel

IPC: G05B23/02

Abstract: Techniques are provided for classifying runs of a recipe within a manufacturing environment. Embodiments monitor a plurality of runs of a recipe to collect runtime data from a plurality of sensors within a manufacturing environment. Qualitative data describing each semiconductor devices produced by the plurality of runs is determined. Embodiments characterize each run into a respective group, based on an analysis of the qualitative data, and generate a data model based on the collected runtime data. A multivariate analysis of additional runtime data collected during at least one subsequent run of the recipe is performed to classify the at least one subsequent run into a first group. Upon classifying the at least one subsequent run, embodiments output for display an interface depicting a ranking sensor types based on the additional runtime data and the description of relative importance of each sensor type for the first group within the data model.

公开(公告)号：US11682668B2

公开(公告)日：2023-06-20

申请号：US17500003

申请日：2021-10-13

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Sanjay Natarajan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/822

CPC classification number: H01L27/088 ,  H01L21/8221 ,  H01L21/823481

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

公开(公告)号：US11658041B2

公开(公告)日：2023-05-23

申请号：US17157546

申请日：2021-01-25

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: H01L21/321 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/3212 ,  H01L21/02183 ,  H01L21/32139 ,  H01L21/762 ,  H01L23/00 ,  H01L23/5226

Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

公开(公告)号：US20230061392A1

公开(公告)日：2023-03-02

申请号：US17897372

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

公开(公告)号：US20220108917A1

公开(公告)日：2022-04-07

申请号：US17487123

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Roey Shaviv ,  Suketu Arun Parikh ,  Feng Chen ,  Lu Chen

IPC: H01L21/768 ,  H01L21/02

Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

公开(公告)号：US20220068917A1

公开(公告)日：2022-03-03

申请号：US17500003

申请日：2021-10-13

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Sanjay Natarajan

IPC: H01L27/088 ,  H01L21/822 ,  H01L21/8234

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

公开(公告)号：US20210404061A1

公开(公告)日：2021-12-30

申请号：US17474193

申请日：2021-09-14

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: C23C16/455 ,  H01L21/02 ,  H01L21/67

Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.

公开(公告)号：US11749561B2

公开(公告)日：2023-09-05

申请号：US17344528

申请日：2021-06-10

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: H01L21/768 ,  H01L21/3213

CPC classification number: H01L21/7682 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76892

Abstract: A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

公开(公告)号：US20230064183A1

公开(公告)日：2023-03-02

申请号：US17897375

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.