公开(公告)号：US20250029874A1

公开(公告)日：2025-01-23

申请号：US18909047

申请日：2024-10-08

Applicant: Applied Materials, Inc.

Inventor： Roey Shaviv ,  Suketu Arun Parikh ,  Feng Chen ,  Lu Chen

IPC: H01L21/768 ,  H01L21/02

Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

公开(公告)号：US20240321633A1

公开(公告)日：2024-09-26

申请号：US18123101

申请日：2023-03-17

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Wu ,  Zheng Ju ,  Feng Chen

IPC: H01L21/768

CPC classification number: H01L21/76861 ,  H01L21/76831 ,  H01L21/76876

Abstract: Methods for depositing ultra-thin films are disclosed. Some embodiments of the disclosure utilize ultra-thin films as barrier layers, liner layers, or nucleation layers to decrease interconnect resistance. Some embodiments advantageously provide continuous films with thicknesses of less than or equal to about 20 Å. Some embodiments advantageously provide films with decreased roughness.

公开(公告)号：US11955382B2

公开(公告)日：2024-04-09

申请号：US17110818

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Kevin Kashefi ,  Alexander Jansen ,  Mehul Naik ,  He Ren ,  Lu Chen ,  Feng Chen

IPC: H01L21/76 ,  H01L21/67 ,  H01L21/768 ,  H01L21/687

CPC classification number: H01L21/76885 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/76829 ,  H01L21/76883 ,  H01L21/68707

Abstract: Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.

公开(公告)号：US11527437B2

公开(公告)日：2022-12-13

申请号：US17022058

申请日：2020-09-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Lanlan Zhong ,  Fuhong Zhang ,  Gang Shen ,  Feng Chen ,  Rui Li ,  Xiangjin Xie ,  Tae Hong Ha ,  Xianmin Tang

IPC: H01L21/768 ,  G11B5/31 ,  C23C16/455

Abstract: Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.

公开(公告)号：US20220122923A1

公开(公告)日：2022-04-21

申请号：US17072806

申请日：2020-10-16

Applicant: Applied Materials, Inc.

Inventor： Lu Chen ,  Seshadri Ganguli ,  Sang Ho Yu ,  Feng Chen

IPC: H01L23/532

Abstract: Embodiments of the disclosure relate to methods and materials for forming barrier layers with enhanced barrier performance and/or reduced via resistance. Some embodiments of the disclosure provide methods for passivating a metal surface by exposing the metal surface to a metal complex comprising an organic ligand with at least three carbon atoms and a double or triple bond that eta bonds with a central metal atom. Some embodiments provide barrier layers within vias which enable a reduction in resistance of at least 25% as a result of thinner barrier layers with equivalent barrier properties.

公开(公告)号：US20220064784A1

公开(公告)日：2022-03-03

申请号：US17011667

申请日：2020-09-03

Applicant: Applied Materials, Inc.

Inventor： Wenjing Xu ,  Gang Shen ,  Yufei Hu ,  Feng Chen ,  Tae Hong Ha

IPC: C23C16/18 ,  H01L21/285 ,  H01L21/02 ,  C23C16/02

Abstract: Methods for selective deposition are described herein. Further, methods for improving selectivity comprising an ammonia plasma pre-clean process are also described. In some embodiments, a silyl amine is used to selectively form a surfactant layer on a dielectric surface. A ruthenium film may then be selectively deposited on a conductive surface. In some embodiments, the ammonia plasma removes oxide contaminations from conductive surfaces without adversely affecting the dielectric surface.

公开(公告)号：US20210351136A1

公开(公告)日：2021-11-11

申请号：US16909148

申请日：2020-06-23

Applicant: Applied Materials, Inc.

Inventor： Gang Shen ,  Feng Chen ,  Yizhak Sabba ,  Tae Hong Ha ,  Xianmin Tang ,  Zhiyuan Wu ,  Wenjing Xu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Described are microelectronic device comprising a dielectric layer formed on a substrate, a feature 206 comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming an microelectronic device comprising the two metal liner film on the barrier layer.

公开(公告)号：US11764157B2

公开(公告)日：2023-09-19

申请号：US17383361

申请日：2021-07-22

Applicant: Applied Materials, Inc.

Inventor： Wenjing Xu ,  Feng Chen ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/5226

Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

公开(公告)号：US20230253248A1

公开(公告)日：2023-08-10

申请号：US18119080

申请日：2023-03-08

Applicant: Applied Materials, Inc.

Inventor： Yang Zhou ,  Yong Jin Kim ,  Ge Qu ,  Zhiyuan Wu ,  Carmen Leal Cervantes ,  Feng Chen ,  Kevin Kashefi ,  Bhaskar Jyoti Bhuyan ,  Drew Phillips ,  Aaron Dangerfield

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L21/28568

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having a formula of H—C≡C—R, wherein R is a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms or a formula of R′C═CR″, wherein R′ and R″ independently include a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

公开(公告)号：US20230121513A1

公开(公告)日：2023-04-20

申请号：US18068469

申请日：2022-12-19

Applicant: APPLIED MATERIALS, INC.

Inventor： Kartik B. Shah ,  Satish Radhakrishnan ,  Karthik Ramanathan ,  Karthikeyan Balaraman ,  Adolph Miller Allen ,  Xinyuan Chong ,  Mitrabhanu Sahu ,  Wenjing Xu ,  Michael Sterling Jackson ,  Weize Hu ,  Feng Chen

IPC: G05B13/02 ,  G05B13/04

Abstract: Process recipe data associated a process to be performed for a substrate at a process chamber is provided as input to a trained machine learning model. A set of process recipe settings for the process that minimizes scratching on one or more surfaces of the substrate is determined based on one or more outputs of the machine learning model. The process is performed for the substrate at the process chamber in accordance with the determined set of process recipe settings.