公开(公告)号：US20180211872A1

公开(公告)日：2018-07-26

申请号：US15874041

申请日：2018-01-18

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan WU ,  Nikolaos BEKIARIS ,  Mehul B. NAIK ,  Jin Hee PARK ,  Mark Hyun LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/288 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53252

Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

公开(公告)号：US20250062160A1

公开(公告)日：2025-02-20

申请号：US18749589

申请日：2024-06-20

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng CHEN ,  Kevin KASHEFI ,  Chengyu LIU

IPC: H01L21/768 ,  H01L21/02

Abstract: A method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.

公开(公告)号：US20240404803A1

公开(公告)日：2024-12-05

申请号：US18647819

申请日：2024-04-26

Applicant: Applied Materials, Inc.

Inventor： Yoon Ah SHIN ,  Jiajie CEN ,  Zhiyuan WU ,  Bencherki MEBARKI ,  Kevin KASHEFI ,  Joung Joo LEE ,  Xianmin TANG

IPC: H01J37/32

Abstract: Embodiments of the present disclosure generally relate to a low temperature non-plasma containing preclean process to selectively remove contaminants from the surface of a substrate, such as halogen containing and/or metal oxide containing contaminants. The non-plasma containing precleaning process is performed at a low temperature by use of a microwave source that is configured to provide microwave energy to the processing gases disposed within a processing chamber. The non-plasma low temperature preclean process is effective in reducing halogen containing residues, such as fluorine and chlorine containing residues formed on a surface of a substrate.

公开(公告)号：US20190157145A1

公开(公告)日：2019-05-23

申请号：US16252100

申请日：2019-01-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.