公开(公告)号：US20240194605A1

公开(公告)日：2024-06-13

申请号：US18534333

申请日：2023-12-08

Applicant: Applied Materials, Inc.

Inventor： Mohammad Mahdi TAVAKOLI ,  Avgerinos V. GELATOS ,  Jiajie CEN ,  Kevin KASHEFI ,  Joung Joo LEE ,  Zhihui LIU ,  Yang ZHOU ,  Zhiyuan WU ,  Meng-Shan WU

IPC: H01L23/532 ,  H01J37/32 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01J37/32357 ,  H01L21/02068 ,  H01L21/76843 ,  H01L21/76877 ,  H01J2237/335

Abstract: A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 Å and 40 Å.

公开(公告)号：US20240186181A1

公开(公告)日：2024-06-06

申请号：US18074335

申请日：2022-12-02

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Qihao ZHU ,  Zheng JU ,  Yang ZHOU ,  Jiajie CEN ,  Feng Q. LIU ,  Zhiyuan WU ,  Feng CHEN ,  Kevin KASHEFI ,  Xianmin TANG ,  Jeffrey W. ANTHIS ,  Mark Joseph SALY

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76849 ,  H01L21/32051 ,  H01L21/76877

Abstract: Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.

公开(公告)号：US20200235006A1

公开(公告)日：2020-07-23

申请号：US16564489

申请日：2019-09-09

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan WU ,  Nikolaos BEKIARIS ,  Mehul B. NAIK ,  Jin Hee PARK ,  Mark Hyun LEE

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/285 ,  H01L21/288 ,  H01L23/528 ,  H01L23/532

Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

公开(公告)号：US20190148150A1

公开(公告)日：2019-05-16

申请号：US16172786

申请日：2018-10-27

Applicant: Applied Materials, Inc.

Inventor： Joung Joo LEE ,  Feng CHEN ,  Zhiyuan WU ,  Atashi BASU ,  Mehul B. NAIK ,  Yufei HU

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/528

Abstract: Methods for forming a capping protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming capping protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal silicide layer on a metal line bounded by a dielectric bulk insulating layer in a back end interconnection structure formed on a substrate in a processing chamber; and forming a dielectric layer on the metal silicide layer.

公开(公告)号：US20240290655A1

公开(公告)日：2024-08-29

申请号：US18115561

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Zheng JU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng Q. LIU ,  Feng CHEN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5226 ,  H01L21/76862 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.

公开(公告)号：US20220336271A1

公开(公告)日：2022-10-20

申请号：US17848162

申请日：2022-06-23

Applicant: Applied Materials, Inc.

Inventor： Mehul B. NAIK ,  Zhiyuan WU

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.

公开(公告)号：US20190067201A1

公开(公告)日：2019-02-28

申请号：US16102533

申请日：2018-08-13

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan WU ,  Meng Chu TSENG ,  Mehul B. NAIK ,  Ben-Li SHEU

IPC: H01L23/532 ,  H01L21/768

Abstract: Methods for forming a copper seed layer having improved anti-migration properties are described herein. In one embodiment, a method includes forming a first copper layer in a feature, forming a ruthenium layer over the first copper layer in the feature, and forming a second copper layer on the ruthenium layer in the feature. The ruthenium layer substantially locks the copper layer there below in place in the feature, preventing substantial physical migration thereof.

公开(公告)号：US20180096888A1

公开(公告)日：2018-04-05

申请号：US15722639

申请日：2017-10-02

Applicant: Applied Materials, Inc.

Inventor： Mehul B. NAIK ,  Zhiyuan WU

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089

Abstract: Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

公开(公告)号：US20240153816A1

公开(公告)日：2024-05-09

申请号：US17980850

申请日：2022-11-04

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng CHEN

IPC: H01L21/768

CPC classification number: H01L21/76855 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882

Abstract: A method for forming a metal liner layer for an interconnect uses a multi-metal deposition process to produce a reduced thickness liner. The back-end-of-the-line packaging process may include forming a metal liner layer by depositing a ruthenium layer with a first thickness of approximately 5 angstroms or less and depositing a first cobalt layer with a second thickness of approximately 20 angstroms or less. In some embodiments, the ruthenium layer may be deposited on a previously formed barrier layer and then undergoes a treatment process before depositing the first cobalt layer. In some embodiments, the first cobalt layer may be deposited on the ruthenium layer or the ruthenium layer maybe deposited on the first cobalt layer. In some embodiments, the ruthenium layer is deposited on the first cobalt layer and a second cobalt layer is deposited on the ruthenium layer.

公开(公告)号：US20180315650A1

公开(公告)日：2018-11-01

申请号：US15498024

申请日：2017-04-26

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.