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    METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY
    11.
    发明申请
    METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY 审中-公开
    制造具有内置加热器和密封件的空心基板的方法

    公开(公告)号：US20130337648A1

    公开(公告)日：2013-12-19

    申请号：US13904207

    申请日：2013-05-29

    Applicant: Bridge Semiconductor Corporation

    Inventor： Charles W.C. LIN ,  Chia-Chung WANG

    IPC: H01L21/48

    CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/00

    Abstract: The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: providing a sacrificial carrier and optionally an electrical pad that extends from the sacrificial carrier in the first vertical direction; providing a dielectric layer that covers the sacrificial carrier in the first vertical direction; removing a selected portion of the sacrificial carrier; attaching a stiffener to the dielectric layer from the second vertical direction; forming a build-up circuitry from the first vertical direction; and removing the remaining portion of the sacrificial carrier to expose electrical contacts from the second vertical direction. A semiconductor device can be mounted on the cavity substrate and electrically connected to the electrical contacts within the built-in cavity of the cavity substrate. The stiffener can provide mechanical support for the build-up circuitry and the semiconductor device.

    Abstract translation: 本发明涉及一种制造空腔衬底的方法。 根据优选实施例，该方法包括：提供牺牲载体和可选地在第一垂直方向上从牺牲载体延伸的电垫; 提供在所述第一垂直方向上覆盖所述牺牲载体的电介质层; 去除牺牲载体的选定部分; 从所述第二垂直方向将加强件附接到所述电介质层; 从第一垂直方向形成积聚电路; 以及去除所述牺牲载体的剩余部分以从所述第二垂直方向露出电触头。 半导体器件可以安装在空腔衬底上并电连接到空腔衬底的内置空腔内的电触点。 加强件可以为积聚电路和半导体器件提供机械支撑。

    THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME
    13.
    发明申请
    THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME 审中-公开
    具有嵌入式半导体器件和内置停止器的热增强半导体组件及其制造方法

    公开(公告)号：US20140048950A1

    公开(公告)日：2014-02-20

    申请号：US13753589

    申请日：2013-01-30

    Applicant: BRIDGE SEMICONDUCTOR CORPORATION

    Inventor： Charles W.C. LIN ,  Chia-Chung WANG

    IPC: H01L23/34 ,  H01L21/50

    CPC classification number: H01L23/5389 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/367 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/4848 ,  H01L2224/73267 ,  H01L2224/8314 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/48465 ,  H01L2924/00

    Abstract: The present invention relates to a thermally enhanced semiconductor assembly and a method of making the same. In accordance with one preferred embodiment, the method includes: forming a stopper on a metal layer; mounting a semiconductor device on the metal layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the metal layer; forming a build-up circuitry that covers the stopper, the semiconductor device and the stiffener; providing a plated through-hole that provides an electrical connection between the build-up circuitry and the metal layer; and removing selected portions of the metal layer to form a thermal pad and a terminal. Accordingly, the thermal pad can provide excellent heat spreading, and the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

    Abstract translation: 本发明涉及一种热增强半导体组件及其制造方法。 根据一个优选实施例，该方法包括：在金属层上形成塞子; 使用所述止动件将半导体器件安装在所述金属层上作为所述半导体器件的布置引导件; 将加强件附接到所述金属层; 形成覆盖止动器，半导体器件和加强件的积聚电路; 提供电镀通孔，其在积聚电路和金属层之间提供电连接; 并且移除所述金属层的选定部分以形成热垫和端子。 因此，散热垫可以提供优异的散热，并且止动器可以准确地限制半导体器件的放置位置，并避免半导体器件与积聚电路之间的电连接故障。

    INTERCONNECT SUBSTRATE WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME
    14.
    发明申请
    INTERCONNECT SUBSTRATE WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME 有权
    具有嵌入式半导体器件和内置停止器的互连衬底及其制造方法

    公开(公告)号：US20140048944A1

    公开(公告)日：2014-02-20

    申请号：US13738314

    申请日：2013-01-10

    Applicant: BRIDGE SEMICONDUCTOR CORPORATION

    Inventor： Charles W.C. LIN ,  Chia-Chung WANG

    IPC: H01L21/58 ,  H01L23/485

    CPC classification number: H01L21/58 ,  H01L23/485 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/12042 ,  H01L2924/15172 ,  H01L2924/171 ,  Y10T428/24917 ,  H01L2924/014 ,  H01L2924/00

    Abstract: The present invention relates to an interconnect substrate with an embedded device, a built-in stopper and dual build-up circuitries and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the dielectric layer; forming a first build-up circuitry and a second build-up circuitry that cover the semiconductor device, the stopper and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

    Abstract translation: 本发明涉及具有嵌入式装置的互连基板，内置止动器和双层叠层电路及其制造方法。 根据本发明的一个优选实施例，该方法包括：在电介质层上形成一个塞子; 使用所述阻挡件将半导体器件安装在所述电介质层上作为所述半导体器件的放置引导件; 将加强件附接到介电层; 形成覆盖半导体器件的第一堆积电路和第二堆积电路，两侧的止动器和加强件; 以及提供在第一和第二堆积电路之间提供电连接的电镀通孔。 因此，止动器可以准确地限制半导体器件的放置位置，并避免半导体器件和积聚电路之间的电连接故障。

    METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY SUBSTRATE MANUFACTURED THEREBY
    15.
    发明申请
    METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY SUBSTRATE MANUFACTURED THEREBY 审中-公开
    使用内置式加热器制造密封基板的方法和制造的CAVITY基板

    公开(公告)号：US20130277832A1

    公开(公告)日：2013-10-24

    申请号：US13738220

    申请日：2013-01-10

    Applicant: BRIDGE SEMICONDUCTOR CORPORATION

    Inventor： Charles W.C. LIN ,  Chia-Chung WANG

    IPC: H01L21/50 ,  H01L23/498

    CPC classification number: H01L21/50 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/115 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15331

    Abstract: The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a coreless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump and a portion of the flange to form a cavity and expose a conductive via of the coreless build-up circuitry from a closed end of the cavity, wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the conductive via. The coreless build-up circuitry provides signal routing for the semiconductor device while the stiffener can provide adequate mechanical support for the coreless build-up circuitry and the semiconductor device.

    Abstract translation: 本发明涉及一种制造空腔衬底的方法。 根据优选实施例，该方法包括：制备包括加强件，凸块/凸缘牺牲载体和粘合剂的支撑板，其中粘合剂将加强件粘合到牺牲载体上; 在与所述凸块和所述加强件接触的支撑板上形成无芯堆积电路; 以及去除所述凸起和所述凸缘的一部分以形成空腔，并且将所述无芯堆积电路的导电通孔从所述空腔的封闭端部暴露出来，其中所述空腔被所述粘合剂横向覆盖和包围。 半导体器件可以安装在空腔衬底上并电连接到导电通孔。 无芯堆积电路为半导体器件提供信号路由，而加强件可为无芯堆积电路和半导体器件提供足够的机械支撑。

    SEMICONDUCTOR ASSEMBLY BOARD WITH BACK-TO-BACK EMBEDDED SEMICONDUCTOR DEVICES AND BUILT-IN STOPPERS
    18.
    发明申请
    SEMICONDUCTOR ASSEMBLY BOARD WITH BACK-TO-BACK EMBEDDED SEMICONDUCTOR DEVICES AND BUILT-IN STOPPERS 审中-公开
    具有背对背嵌入式半导体器件和内置停止器的半导体组件板

    公开(公告)号：US20140048955A1

    公开(公告)日：2014-02-20

    申请号：US14062939

    申请日：2013-10-25

    Applicant: Bridge Semiconductor Corporation

    Inventor： Charles W.C. LIN ,  Chia-Chung WANG

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8314 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/19 ,  H01L2924/00

    Abstract: In a preferred embodiment, a semiconductor assembly board with back-to-back embedded devices and built-in stoppers includes an intermediate layer, a first stopper, a first semiconductor device, a first core layer, a second stopper, a second semiconductor device, a second core layer, a first build-up circuitry, a second build-up circuitry and a plated through hole. The first and second semiconductor devices are mounted on opposite surfaces of the intermediate layer using the first and second stoppers as placement guides that are laterally aligned with peripheral edges of the first and second semiconductor devices. The first and second core layers laterally cover the first and second semiconductor devices. The first and second build-up circuitries cover the semiconductor devices and the core layers in the opposite vertical directions and provide signal routing for the first and second semiconductor devices.

    Abstract translation: 在优选实施例中，具有背对背嵌入式装置和内置止动件的半导体组装板包括中间层，第一止动件，第一半导体器件，第一芯层，第二阻挡件，第二半导体器件， 第二芯层，第一堆叠电路，第二堆积电路和电镀通孔。 使用第一和第二挡块将第一和第二半导体器件安装在中间层的相对表面上，作为与第一和第二半导体器件的外围边缘横向对准的放置引导件。 第一和第二芯层横向覆盖第一和第二半导体器件。 第一和第二堆叠电路在相反的垂直方向上覆盖半导体器件和核心层，并为第一和第二半导体器件提供信号路由。

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