公开(公告)号：US09348595B1

公开(公告)日：2016-05-24

申请号：US14578516

申请日：2014-12-22

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/3851 ,  G06F9/46 ,  G06F11/30 ,  G06F11/3466 ,  G06F2201/865

Abstract: A method includes, in a processor that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.

Abstract translation: 一种方法包括在执行程序代码指令的处理器中监视遍历流程控制轨迹的指令的重复序列的指令，以便构建被监视指令的寄存器访问的规范。 基于该规范，调用多个硬件线程来至少部分地并行地执行重复指令序列的相应段。 在执行期间，至少一个段中的指令的监视继续。

公开(公告)号：US10296350B2

公开(公告)日：2019-05-21

申请号：US14673889

申请日：2015-03-31

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F9/30

Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

公开(公告)号：US10013255B2

公开(公告)日：2018-07-03

申请号：US15077936

申请日：2016-03-23

Applicant: Centipede Semi Ltd.

Inventor： Jonathan Friedmann ,  Ido Goren ,  Shay Koren ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/38 ,  G06F9/40 ,  G06F9/45 ,  G06F9/30 ,  G06F8/41 ,  G06F9/455

CPC classification number: G06F9/30058 ,  G06F8/443 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3867 ,  G06F9/45516

Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

公开(公告)号：US09715390B2

公开(公告)日：2017-07-25

申请号：US14690424

申请日：2015-04-19

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F12/0831

CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/455 ,  G06F9/46 ,  G06F12/0833

Abstract: A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

公开(公告)号：US20160291979A1

公开(公告)日：2016-10-06

申请号：US14673889

申请日：2015-03-31

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30065 ,  G06F9/3808 ,  G06F9/3838

Abstract: A method includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

Abstract translation: 一种方法包括在处理程序代码指令的处理器中，通过第一硬件线程处理一个或多个指令。 在检测到已经为第一线程获取定义为并行化点的指令时，调用第二硬件线程以至少部分地与第一硬件线程对指令的处理并行地处理指令中的至少一个。

公开(公告)号：US09135015B1

公开(公告)日：2015-09-15

申请号：US14583119

申请日：2014-12-25

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F11/1402 ,  G06F11/30 ,  G06F11/302 ,  G06F11/3055 ,  G06F11/3065 ,  G06F11/3466

Abstract: A method includes, in a processor that executes instructions of program code, monitoring the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions. In response to detecting a branch mis-prediction in the monitored instructions, the specification is corrected so as to compensate for the branch mis-prediction. Execution of the repetitive sequence is parallelized based on the corrected specification.

Abstract translation: 一种方法包括在执行程序代码的指令的处理器中监视指令的重复序列的段中的指令，以便构建被监视指令的寄存器访问的规范。 响应于检测到所监视的指令中的分支误差预测，修正说明书以补偿分支误预测。 基于修正后的规格，重复序列的执行是并行化的。

公开(公告)号：US10452400B2

公开(公告)日：2019-10-22

申请号：US15904474

申请日：2018-02-26

Applicant: Centipede Semi Ltd.

Inventor： Avishai Tvila ,  Alberto Mandler

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor includes a pipeline and a multi-bank Branch-Target Buffer (BTB). The pipeline is configured to process program instructions including branch instructions. The multi-bank BTB includes a plurality of BTB banks and is configured to store learned Target Addresses (TAs) of one or more of the branch instructions in the plurality of the BTB banks, to receive from the pipeline simultaneous requests to retrieve respective TAs, and to respond to the requests using the plurality of the BTB banks in the same clock cycle.

公开(公告)号：US20190265977A1

公开(公告)日：2019-08-29

申请号：US15904474

申请日：2018-02-26

Applicant: Centipede Semi Ltd.

Inventor： Avishai Tvila ,  Alberto Mandler

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor includes a pipeline and a multi-bank Branch-Target Buffer (BTB). The pipeline is configured to process program instructions including branch instructions. The multi-bank BTB includes a plurality of BTB banks and is configured to store learned Target Addresses (TAs) of one or more of the branch instructions in the plurality of the BTB banks, to receive from the pipeline simultaneous requests to retrieve respective TAs, and to respond to the requests using the plurality of the BTB banks in the same clock cycle.

公开(公告)号：US10296346B2

公开(公告)日：2019-05-21

申请号：US14673884

申请日：2015-03-31

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F9/46

Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.

公开(公告)号：US10180841B2

公开(公告)日：2019-01-15

申请号：US15007299

申请日：2016-01-27

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F9/46 ,  G06F11/30 ,  G06F11/34

Abstract: A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions. The monitoring unit is configured to evaluate a termination criterion based on the monitored instructions while monitoring the processing and recording the respective monitoring tables, and upon meeting the termination criterion, to terminate the monitoring before completion of the recording of the respective monitoring tables for at least second sequences of the instructions.