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公开(公告)号：US20170123798A1
公开(公告)日：2017-05-04
申请号：US15077940
申请日：2016-03-23
Applicant: Centipede Semi Ltd.
Inventor： Jonathan Friedmann , Ido Goren , Shay Koren , Noam Mizrahi , Alberto Mandler
CPC classification number: G06F9/30058 , G06F8/443 , G06F9/30061 , G06F9/30065 , G06F9/30072 , G06F9/30079 , G06F9/3808 , G06F9/3842 , G06F9/3844 , G06F9/3867 , G06F9/45516
Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes at least first and second conditional branch instructions that conditionally diverge execution of the instructions into a plurality of flow-control traces that differ from one another in multiple instructions and converge at a given instruction. A second block of instructions, which is logically equivalent to the first block but replaces the plurality of flow-control traces by a reduced set of one or more flow-control traces, having fewer flow-control traces than the first block, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.
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公开(公告)号：US20170123797A1
公开(公告)日：2017-05-04
申请号：US15077936
申请日：2016-03-23
Applicant: Centipede Semi Ltd.
Inventor： Jonathan Friedmann , Ido Goren , Shay Koren , Noam Mizrahi , Alberto Mandler
CPC classification number: G06F9/30058 , G06F8/443 , G06F9/30061 , G06F9/30065 , G06F9/30072 , G06F9/30079 , G06F9/3808 , G06F9/3842 , G06F9/3844 , G06F9/3867 , G06F9/45516
Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.
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公开(公告)号：US10013255B2
公开(公告)日：2018-07-03
申请号：US15077936
申请日：2016-03-23
Applicant: Centipede Semi Ltd.
Inventor： Jonathan Friedmann , Ido Goren , Shay Koren , Noam Mizrahi , Alberto Mandler
CPC classification number: G06F9/30058 , G06F8/443 , G06F9/30061 , G06F9/30065 , G06F9/30072 , G06F9/30079 , G06F9/3808 , G06F9/3842 , G06F9/3844 , G06F9/3867 , G06F9/45516
Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.
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公开(公告)号：US20180004627A1
公开(公告)日：2018-01-04
申请号：US15196071
申请日：2016-06-29
Applicant: Centipede Semi Ltd.
Inventor： Shay Koren , Arie Hacohen Ben Porat , Ido Goren , Noam Mizrahi , Jonathan Friedmann
CPC classification number: G06F11/3644 , G06F9/30058 , G06F9/3808 , G06F9/3838 , G06F9/3861 , G06F11/3466
Abstract: A processor includes an instruction pipeline and control circuitry. The instruction pipeline is configured to process instructions of program code. The control circuitry is configured to monitor the processed instructions at run-time, to construct an invocation data structure comprising multiple entries, wherein each entry (i) specifies an initial instruction that is a target of a branch instruction, (ii) specifies a portion of the program code that follows one or more possible flow-control traces beginning from the initial instruction, and (iii) specifies, for each possible flow-control trace specified in the entry, a next entry that is to be processed following processing of that possible flow-control trace, and to configure the instruction pipeline to process segments of the program code, by continually traversing the entries of the invocation data structure.
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