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    Dynamic multiphase injection-locked phase rotator for electro-optical transceiver
    11.
    发明授权
    Dynamic multiphase injection-locked phase rotator for electro-optical transceiver 有权

    公开(公告)号：US11063595B1

    公开(公告)日：2021-07-13

    申请号：US16878069

    申请日：2020-05-19

    Applicant: Cisco Technology, Inc.

    Inventor： Yudong Zhang ,  Romesh Kumar Nandwana ,  Kadaba Lakshmikumar

    IPC: H03L7/081 ,  H04B1/38

    Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.

    Photodiode cathode biasing
    16.
    发明授权
    Photodiode cathode biasing 有权

    公开(公告)号：US11552600B2

    公开(公告)日：2023-01-10

    申请号：US16553950

    申请日：2019-08-28

    Applicant: Cisco Technology, Inc.

    Inventor： Alexander C. Kurylak ,  Kadaba Lakshmikumar

    IPC: H03F3/08 ,  H04B10/69

    Abstract: In one embodiment, stable and controlled circuit element biasing is provided in a circuit comprising a voltage source operable to output a first voltage, a reference voltage source operable to output a reference voltage, a circuit element biased, during operation, by the first voltage at a first end and by a second voltage at a second end, a voltage controller coupled to the second end of the circuit element, wherein the voltage controller is operable to adjust the second voltage based on a gain output, a gain controller operable to receive the reference voltage as a first input and the second voltage as a second input, wherein the gain controller is operable to generate, at an output of the gain controller, the gain output based on the second voltage and the reference voltage, and a feedback loop that extends from the output of the gain controller, through the voltage controller, and to the second input.

    HYBRID FRACTIONAL-N SAMPLING PHASE LOCKED LOOP (PLL) WITH ACCURATE DIGITAL-TO-TIME CONVERTER (DTC) CALIBRATION
    20.
    发明公开
    HYBRID FRACTIONAL-N SAMPLING PHASE LOCKED LOOP (PLL) WITH ACCURATE DIGITAL-TO-TIME CONVERTER (DTC) CALIBRATION 审中-公开

    公开(公告)号：US20240056085A1

    公开(公告)日：2024-02-15

    申请号：US17887709

    申请日：2022-08-15

    Applicant: Cisco Technology, Inc.

    Inventor： Abhishek Bhat ,  Romesh Kumar Nandwana ,  Pavan Kumar Hanumolu ,  Kadaba Lakshmikumar

    IPC: H03L7/099

    CPC classification number: H03L7/099

    Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.

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