公开(公告)号：US20200218523A1

公开(公告)日：2020-07-09

申请号：US16277178

申请日：2019-02-15

Applicant: Graphcore Limited

Inventor： Mark Lloyd Pupilli ,  David Lacey

IPC: G06F8/41 ,  G06N3/08 ,  G06F16/901

Abstract: A method for generating a program to run on multiple tiles. The method comprises: receiving an input graph comprising data nodes, compute vertices and edges; receiving an initial tile-mapping specifying which data nodes and vertices are allocated to which tile; and determining a subgraph of the input graph that meets one or more heuristic rules. The rules comprises: the subgraph comprises at least one data node, the subgraph spans no more than a threshold number of tiles in the initial tile-mapping, and the subgraph comprises at least a minimum number of edges outputting to one or more vertices on one or more other tiles. The method further comprises adapting the initial mapping to migrate the data nodes and any vertices of the determined subgraph to said one or more other tiles, and compiling the executable program from the graph with the vertices and data nodes allocated by the adapted mapping.

公开(公告)号：US12141092B2

公开(公告)日：2024-11-12

申请号：US17658124

申请日：2022-04-06

Applicant: Graphcore Limited

Inventor： Simon Christian Knowles ,  Daniel John Pelham Wilkinson ,  Richard Luke Southwell Osborne ,  Alan Graham Alexander ,  Stephen Felix ,  Jonathan Mangnall ,  David Lacey

IPC: G06F15/173 ,  G06F8/41 ,  G06F9/38 ,  G06F15/80

Abstract: The invention relates to a computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising one or more computer executable instruction which, when executed, implements: a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time; and a switch control function which causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined receive time.

公开(公告)号：US11720332B2

公开(公告)日：2023-08-08

申请号：US16527410

申请日：2019-07-31

Applicant: Graphcore Limited

Inventor： David Lacey ,  Godfrey Da Costa

IPC: G06F8/30 ,  G06F8/41

CPC classification number: G06F8/41

Abstract: A method for generating an executable program to run on one or more processor modules. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and edges; and compiling the graph into an executable program including one or more types of multi-access instruction each of which performs at least two memory access (load and/or store) operations in a single instruction. The memory on each processor module comprises multiple memory banks whereby the same bank cannot be accessed by different load or store operations in the same instruction. The compilation comprises assigning instances of the multi-access instructions to implement at least some of the graph edges, and allocating the data to memory addresses within different ones of the banks. The allocating is performed subject to one or more constraints, including at least that different load/store operations should not access the same memory bank in the same instruction.

公开(公告)号：US11263081B2

公开(公告)日：2022-03-01

申请号：US16419361

申请日：2019-05-22

Applicant: Graphcore Limited

Inventor： David Lacey ,  Daniel John Pelham Wilkinson

IPC: G06F11/14 ,  G06F1/30 ,  G06F7/58 ,  G06F9/38 ,  G06F9/52

Abstract: A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at successive points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.

公开(公告)号：US11262787B2

公开(公告)日：2022-03-01

申请号：US16744249

申请日：2020-01-16

Applicant: Graphcore Limited

Inventor： Simon Christian Knowles ,  Daniel John Pelham Wilkinson ,  Richard Luke Southwell Osborne ,  Alan Graham Alexander ,  Stephen Felix ,  Jonathan Mangnall ,  David Lacey

IPC: G06F1/12 ,  G06F9/52 ,  G06F9/30 ,  G06F9/54 ,  G06F9/38 ,  G06F15/173 ,  G06N20/00

Abstract: The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal a send instruction to transmit at least one data packet at a predetermined transmit time, relative to the synchronisation signal, destined for a recipient processing unit but having no destination identifier, and a local program allocated to the recipient processing unit is scheduled to execute at a predetermined switch time a switch control instruction to control the switching circuitry to connect its processing unit wire to the switching fabric to receive the data packet at a receive time.

公开(公告)号：US10936008B2

公开(公告)日：2021-03-02

申请号：US15886009

申请日：2018-02-01

Applicant: Graphcore Limited

Inventor： Simon Christian Knowles ,  Daniel John Pelham Wilkinson ,  Richard Luke Southwell Osborne ,  Alan Graham Alexander ,  Stephen Felix ,  Jonathan Mangnall ,  David Lacey

IPC: G06F1/12 ,  G06F3/06 ,  G06F13/40

Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient processing unit executes a switch control instruction from its local program to control its switching circuitry to connect its input set of wires to the switching fabric to receive the data packet at a receive time, the transmit time and, switch time and receive time being governed by the common clock with respect to the synchronisation signal.

公开(公告)号：US10691432B1

公开(公告)日：2020-06-23

申请号：US16277178

申请日：2019-02-15

Applicant: Graphcore Limited

Inventor： Mark Lloyd Pupilli ,  David Lacey

IPC: G06F8/41 ,  G06F16/901 ,  G06N3/08

Abstract: A method for generating a program to run on multiple tiles. The method comprises: receiving an input graph comprising data nodes, compute vertices and edges; receiving an initial tile-mapping specifying which data nodes and vertices are allocated to which tile; and determining a subgraph of the input graph that meets one or more heuristic rules. The rules comprises: the subgraph comprises at least one data node, the subgraph spans no more than a threshold number of tiles in the initial tile-mapping, and the subgraph comprises at least a minimum number of edges outputting to one or more vertices on one or more other tiles. The method further comprises adapting the initial mapping to migrate the data nodes and any vertices of the determined subgraph to said one or more other tiles, and compiling the executable program from the graph with the vertices and data nodes allocated by the adapted mapping.

公开(公告)号：US20200012536A1

公开(公告)日：2020-01-09

申请号：US16276834

申请日：2019-02-15

Applicant: Graphcore Limited

Inventor： David Lacey ,  Daniel John Pelham Wilkinson ,  Richard Luke Southwell Osborne ,  Matthew David Fyles

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F16/901

Abstract: A system comprising: a first subsystem comprising one or more first processors, and a second subsystem comprising one or more second processors. The second subsystem is configured to process code over a series of steps delineated by barrier synchronizations, and in a current step, to send a descriptor to the first subsystem specifying a value of each of one or more parameters of each of one or more interactions that the second subsystem is programmed to perform with the first subsystem via an inter-processor interconnect in a subsequent step. The first subsystem is configured to execute a portion of code to perform one or more preparatory operations, based on the specified values of at least one of the one or more parameters of each interaction as specified by the descriptor, to prepare for said one or more interactions prior to the barrier synchronization leading into the subsequent phase.

公开(公告)号：US11940940B2

公开(公告)日：2024-03-26

申请号：US17658944

申请日：2022-04-12

Applicant: Graphcore Limited

Inventor： Daniel Wilkinson ,  Stephen Felix ,  Simon Knowles ,  Graham Cunningham ,  David Lacey

IPC: G06F13/40 ,  G06F9/30 ,  G06F9/52

CPC classification number: G06F13/4022 ,  G06F9/30079 ,  G06F9/522 ,  G06F13/4027

Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.

公开(公告)号：US11768735B2

公开(公告)日：2023-09-26

申请号：US17651012

申请日：2022-02-14

Applicant: Graphcore Limited

Inventor： David Lacey ,  Daniel John Pelham Wilkinson

IPC: G06F11/14 ,  G06F9/52 ,  G06F11/36

CPC classification number: G06F11/1407 ,  G06F9/522 ,  G06F11/141 ,  G06F11/3632 ,  G06F11/3636

Abstract: A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at one or more points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.