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公开(公告)号：US20250077181A1
公开(公告)日：2025-03-06
申请号：US18460322
申请日：2023-09-01
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , James S. Ignowski
Abstract: A computing system that includes an attention engine is disclosed. The attention engine is an in-memory computing module that may be used to accelerate attention operations. The attention engine includes a dot product circuit and a multiplier circuit, which together are used to perform matrix generation and matrix multiplication in the analog domain. Performing matrix multiplication in the analog domain may be faster and/or consume less power than performing matrix multiplication in the digital domain.
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公开(公告)号：US20240170064A1
公开(公告)日：2024-05-23
申请号：US18420978
申请日：2024-01-24
Applicant: Hewlett Packard Enterprise Development LP
CPC classification number: G11C15/046 , H03K19/20
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.
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公开(公告)号：US20240153555A1
公开(公告)日：2024-05-09
申请号：US18411222
申请日：2024-01-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Catherine Graves , Giacomo Pedretti , Sergey Serebryakov , John Paul Strachan
CPC classification number: G11C13/004 , G06N7/01 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C15/04
Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.
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公开(公告)号：US11899965B2
公开(公告)日：2024-02-13
申请号：US17691642
申请日：2022-03-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Thomas Maurits M. Van Vaerenbergh , Catherine E. Graves
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06N3/063
Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.
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公开(公告)号：US20230410902A1
公开(公告)日：2023-12-21
申请号：US17841532
申请日：2022-06-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
CPC classification number: G11C15/046 , H03K19/20
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.
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Patent Agency Ranking
公开(公告)号：US20250054547A1
公开(公告)日：2025-02-13
申请号：US18447776
申请日：2023-08-10
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Giacomo Pedretti , Todd Richmond , Thomas Van Vaerenbergh
Abstract: Examples of the presently disclosed technology provide CAM-based circuits specially constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. With the strategic addition of auxiliary counting and logic circuits that evaluate match line voltage outputs of a CAM at k discrete times in order to determine whether a counted number of matches returned by a match line satisfies a pre-determine parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technology can leverage a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses. Accordingly, this extremely versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time, and with less hardware and power consumption than existing hardware accelerators.
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17.发明授权公开(公告)号：US12119061B2
公开(公告)日：2024-10-15
申请号：US17841542
申请日：2022-06-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
CPC classification number: G11C15/046 , G06F3/0604 , G06F16/3341 , H03K19/20
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells. The method further includes applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause, randomly selecting one matched match line, determining a selected clause from one or more violated clause, and altering one or more literals within the interpretation using a break count for each variable of the selected clause.
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公开(公告)号：US11923009B2
公开(公告)日：2024-03-05
申请号：US17841532
申请日：2022-06-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
CPC classification number: G11C15/046 , H03K19/20
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.
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公开(公告)号：US11783907B2
公开(公告)日：2023-10-10
申请号：US17514847
申请日：2021-10-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Giacomo Pedretti , John Paul Strachan , Catherine Graves
CPC classification number: G11C27/005 , G11C15/046
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
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公开(公告)号：US20230289090A1
公开(公告)日：2023-09-14
申请号：US17691642
申请日：2022-03-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Thomas Maurits M. Van Vaerenbergh , Catherine E. Graves
CPC classification number: G06F3/0655 , G06N3/063 , G06F3/0604 , G06F3/0673
Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.
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