公开(公告)号：US09941023B2

公开(公告)日：2018-04-10

申请号：US15313751

申请日：2014-06-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Lidia Warnes ,  Melvin K. Benedict ,  Andrew C. Walton

IPC: G11C29/00 ,  G11C14/00 ,  G11C5/14

CPC classification number: G11C29/70 ,  G11C5/04 ,  G11C5/148 ,  G11C14/0018 ,  G11C29/44 ,  G11C29/808 ,  G11C29/835 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.

公开(公告)号：US20170336976A1

公开(公告)日：2017-11-23

申请号：US15535378

申请日：2014-12-12

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Naveen Muralimanohar ,  Lidia Warnes

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G06F21/79 ,  G06F2221/2101 ,  G06F2221/2141 ,  G06F2221/2151 ,  G11C13/003

Abstract: Example implementations relate to determining resting times for memory blocks. In example implementations, accessed memory blocks in a cross-point non-volatile memory may be tracked. A respective resting time for each of the accessed memory blocks may be determined. An access command may be prevented from being issued to one of the accessed memory blocks.

公开(公告)号：US10891185B2

公开(公告)日：2021-01-12

申请号：US15314831

申请日：2014-08-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Lidia Warnes ,  Melvin K. Benedict ,  Andrew C. Walton

IPC: G11C29/06 ,  G06F11/10 ,  G11C29/44 ,  G11C29/50 ,  G11C29/12 ,  G06F5/06 ,  G06F11/07 ,  G11C11/41

Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

公开(公告)号：US10481807B2

公开(公告)日：2019-11-19

申请号：US15535828

申请日：2014-12-22

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K. Benedict ,  Lidia Warnes

IPC: G06F11/00 ,  G06F3/06 ,  G06F1/30 ,  G06F11/14 ,  G06F11/30

Abstract: Example implementations relate to generating statuses for data images. In example implementations, an event, in response to which a save operation is initiated on a memory module, may be identified. A data image may be generated during the save operation. A status may be generated for the generated data mage. The status may include an event portion indicative of the identified event, and a completion portion indicative of whether the save operation was completed.

公开(公告)号：US09778982B2

公开(公告)日：2017-10-03

申请号：US15034651

申请日：2013-12-09

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Lidia Warnes ,  Erin A Handgen ,  Andrew C. Walton

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/128 ,  G06F12/0875 ,  G06F11/20

CPC classification number: G06F11/106 ,  G06F11/1016 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/128 ,  G06F2211/1088 ,  G06F2212/1032 ,  G06F2212/466 ,  G06F2212/60 ,  G06F2212/621

Abstract: Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.

公开(公告)号：US20170199785A1

公开(公告)日：2017-07-13

申请号：US15314902

申请日：2014-07-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Chris Michael Brueggen ,  Lidia Warnes

IPC: G06F11/10 ,  G06F11/20 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/106 ,  G06F11/2094 ,  G06F2201/81

Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.