公开(公告)号：US20240179853A1

公开(公告)日：2024-05-30

申请号：US18519524

申请日：2023-11-27

Applicant: IBIDEN CO., LTD.

Inventor： Susumu KAGOHASHI ,  Jun SAKAI

IPC: H05K3/46 ,  H05K1/03 ,  H05K3/10 ,  H05K3/42

CPC classification number: H05K3/4605 ,  H05K1/0306 ,  H05K3/108 ,  H05K3/423

Abstract: A wiring substrate includes an insulating layer including inorganic particles and resin, a seed layer formed on a surface of the insulating layer, and a conductor layer including a conductor pattern and formed on the seed layer. The surface of the insulating layer is a roughened surface formed such that the roughened surface of the insulating layer has exposed portions of the inorganic particles and resin with gaps at interfaces where the inorganic particles and the resin are in contact, and the seed layer is formed on the roughened surface of the insulating layer such that the seed layer is formed along the exposed portions of the inorganic particles and resin exposed on the roughened surface of the insulating layer and is not formed in the gaps at the interfaces where the inorganic particles and the resin are in contact.

公开(公告)号：US20230422408A1

公开(公告)日：2023-12-28

申请号：US18338661

申请日：2023-06-21

Applicant: IBIDEN CO., LTD.

Inventor： Jun SAKAI ,  Kyohei YOSHIKAWA

IPC: H05K3/42 ,  H05K3/18

CPC classification number: H05K3/423 ,  H05K3/429 ,  H05K3/188

Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening extending from a first surface to a second surface of the resin insulating layer and laminated on the first conductor layer, a second conductor layer formed on the first surface of the resin insulating layer such that the first conductor layer is facing the second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the opening of the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer and that the via conductor and the second conductor layer include a seed layer and an electrolytic plating layer formed on the seed layer. The seed layer includes an amorphous metal in a range of 5 wt % to 80 wt %.

公开(公告)号：US20230319987A1

公开(公告)日：2023-10-05

申请号：US18191062

申请日：2023-03-28

Applicant: IBIDEN CO., LTD.

Inventor： Jun SAKAI ,  Shiho SHIMADA

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/18

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K3/424 ,  H05K3/188 ,  H05K2201/09827 ,  H05K2201/096

Abstract: A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer and including a conductor circuit, and a via conductor formed in an opening formed in the insulating layer and connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first layer and a second layer formed on the first layer, the first layer has a width greater than a width of the second layer in cross section of the conductor circuit in the second conductor layer and that the electrolytic plating layer has a width greater than the width of the first layer in cross section of the conductor circuit in the second conductor layer.

公开(公告)号：US20240431031A1

公开(公告)日：2024-12-26

申请号：US18748790

申请日：2024-06-20

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Jun SAKAI ,  Shiho SHIMADA

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/16

Abstract: A printed wiring board includes a first insulating layer, a connection conductor layer including wiring, a second insulating layer covering the connection conductor layer, a conductor layer including first and second electrodes such that the first electrode mounts a first electronic component and the second electrode mounts a second electronic component, and via conductors including first and second via conductors. The first via conductor connects the first electrode and wiring. The second via conductor connects the second electrode and wiring. The conductor layer includes a seed layer and an electrolytic plating layer. The seed layer includes a first layer formed on the first insulating layer and a second layer formed on the first layer, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer of the seed layer.

公开(公告)号：US20250008651A1

公开(公告)日：2025-01-02

申请号：US18753887

申请日：2024-06-25

Applicant: IBIDEN CO., LTD.

Inventor： Susumu KAGOHASHI ,  Jun SAKAI

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/16 ,  H05K3/42

Abstract: A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor, a second conductor layer formed on the insulating layer, and a via conductor formed in the insulating layer such that the via conductor is penetrating through the insulating layer and connecting the first and second conductor layers. The insulating layer has a via hole in which the via conductor is formed such that inner wall surface in the via hole has a first inclined surface decreasing in diameter from the second conductor layer to a middle portion of the via hole in a thickness direction of the insulating layer, a second inclined surface decreasing in diameter from the middle portion to the first conductor layer with a smaller diameter than an end part of the first inclined surface in the middle portion, and a step surface connecting the first and second inclined surfaces.

公开(公告)号：US20240389231A1

公开(公告)日：2024-11-21

申请号：US18661198

申请日：2024-05-10

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Jun SAKAI ,  Takuya INISHI

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/40 ,  H05K3/46

Abstract: A printed wiring board includes a mounting conductor layer including first and second electrodes, a connection conductor layer including connection wirings such that the connection wirings connect the first and second electrodes, a resin insulating layer formed between the mounting conductor layer and the connection conductor layer and having openings, and connection via conductors formed in the openings of the resin insulating layer and including first and second connection via conductors such that the first connection via conductors electrically connect the first electrodes and the connection wirings and the second connection via conductors electrically connect the second electrodes and the connection wirings. The resin insulating layer includes inorganic particles and resin. The inorganic particles include first inorganic particles forming inner wall surfaces in the openings and second inorganic particles embedded in the resin insulating layer. Shapes of the first inorganic particles are different from shapes of the second inorganic particles.

公开(公告)号：US20240363541A1

公开(公告)日：2024-10-31

申请号：US18646819

申请日：2024-04-26

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Susumu KAGOHASHI ,  Jun SAKAI ,  Kyohei YOSHIKAWA

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5383 ,  H01L21/4857

Abstract: A wiring substrate includes a first build-up part including first insulating layers, first conductor layers, and first via conductors, and a second build-up part including second insulating layers and second conductor layers. The minimum wiring width and minimum inter-wiring distance in the first conductor layers are smaller than the minimum wiring width and minimum inter-wiring distance in the second conductor layers. The first conductor layers and via conductors include a first layer and a second layer formed on the first layer. The first layer includes a lower layer including a sputtering film including an alloy including copper, aluminum, and at least one element selected from nickel, zinc, gallium, silicon, and magnesium, and an upper layer including a sputtering film including copper. The lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors.

公开(公告)号：US20240251510A1

公开(公告)日：2024-07-25

申请号：US18420841

申请日：2024-01-24

Applicant: IBIDEN CO., LTD.

Inventor： Susumu KAGOHASHI ,  Jun SAKAI ,  Kyohei YOSHIKAWA

IPC: H05K3/42 ,  H05K3/14 ,  H05K3/18

CPC classification number: H05K3/42 ,  H05K3/146 ,  H05K3/188 ,  H05K2203/0723

Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer, a second conductor layer, and a via conductor formed in an opening of the insulating layer and connecting the first conductor and second conductor layers. The second conductor layer and via conductor include a seed layer having a first portion formed on the surface of the insulating layer, a second portion formed on an inner wall surface in the opening, and a third portion formed on a portion of the first conductor layer exposed by the opening. A thickness of the first portion is greater than a thickness of the second portion and a thickness of the third portion. The seed layer includes a first layer including an alloy including copper, aluminum and one or more metals selected from nickel, zinc, gallium, silicon, and magnesium, and a second layer formed on the first layer and including copper.

公开(公告)号：US20240243049A1

公开(公告)日：2024-07-18

申请号：US18414955

申请日：2024-01-17

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Masashi KUWABARA ,  Jun SAKAI ,  Takuya INISHI

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49894

Abstract: A wiring substrate includes a first build-up part including first insulating layers and conductor layers, a second build-up part laminated to the first part and including second insulating layers and conductor layers, and via conductors including first via conductors in the first insulating layers and second via conductors in the second insulating layers. The first part is positioned closer to first surface side of the substrate than the second part. The first conductor layers include wirings having wiring width and inter-wiring distance that are smaller than wiring width and inter-wiring distance of wirings in the second conductor layers. The first insulating layers include resin and inorganic particles including first particles forming inner wall surfaces in through holes and second particles embedded in the first insulating layers having different shapes from the first particles. Each first conductor layers and via conductors includes a metal film layer and a plating film layer.

公开(公告)号：US20240049398A1

公开(公告)日：2024-02-08

申请号：US18365453

申请日：2023-08-04

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Jun SAKAI

IPC: H05K3/24 ,  H05K3/46 ,  H05K3/10 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/241 ,  H05K3/4605 ,  H05K3/108 ,  H05K1/115 ,  H05K1/092

Abstract: A wiring substrate includes an insulating layer, and a conductor layer formed on a surface of the insulating layer and including wiring patterns such that the conductor layer has a polished surface on the opposite side with respect to the insulating layer and includes an upper layer including a plating film and a lower layer including a seed layer for the plating film and directly formed on the surface of the insulating layer. The conductor layer is formed such that a ratio of a thickness of the lower layer to a thickness of the conductor layer is 2.5% or less, the wiring patterns have the minimum wiring width of 5 μm or less and the minimum inter-wiring distance of 7 μm or less, and each of the wiring patterns has an aspect ratio in a range of 2.0 to 4.0.