公开(公告)号：US10097918B2

公开(公告)日：2018-10-09

申请号：US13747496

申请日：2013-01-23

Applicant: Infineon Technologies AG

Inventor： Thomas Spoettl ,  Horst Theuss

IPC: H04R9/08 ,  H04R11/04 ,  H04R17/02 ,  H04R19/04 ,  H04R21/02 ,  H04R3/00 ,  H04R31/00 ,  H04R19/00

Abstract: In various embodiments, a method for manufacturing a chip arrangement, the method including bonding a microphone chip to a first carrier, the microphone chip including a microphone structure, depositing adhesive material laterally disposed from the microphone structure, and arranging the microphone structure into a cavity of a second carrier such that the adhesive material fixes the microphone chip to the cavity of the second carrier.

公开(公告)号：US09927498B2

公开(公告)日：2018-03-27

申请号：US14297685

申请日：2014-06-06

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Horst Theuss ,  Alexander Spielbauer ,  Ingrid Bollmann

IPC: G01R33/06 ,  G01R33/00

CPC classification number: G01R33/06 ,  G01R33/0052 ,  H01L2224/48091 ,  H01L2924/181 ,  Y10T29/49021 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: In one implementation, a magnetic sensor device used for sensing a static or dynamic magnetic field includes a ring-shaped magnet, a sensor chip arranged in an opening of the ring-shaped magnet, and a leadframe, with the ring-shaped magnet and the sensor chip directly disposed on the leadframe. The sensor chip may further include a carrier with a stepwise configuration having two or more different planes with the ring-shaped magnet and the sensor chip disposed on different planes.

公开(公告)号：US09859332B2

公开(公告)日：2018-01-02

申请号：US14792289

申请日：2015-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Horst Theuss ,  Albert Auburger

IPC: H01L43/06 ,  H01L27/22 ,  G01R33/00 ,  G01R33/07 ,  G01R33/09 ,  H01L43/14 ,  H01L43/04

CPC classification number: H01L27/22 ,  G01R33/0005 ,  G01R33/072 ,  G01R33/091 ,  H01L43/04 ,  H01L43/14

Abstract: The invention relates to a semiconductor component (100) comprising a semiconductor chip (10) configured as a wafer level package, a magnetic field sensor (11) being integrated into said semiconductor chip.

公开(公告)号：US09818665B2

公开(公告)日：2017-11-14

申请号：US14193480

申请日：2014-02-28

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Horst Theuss

IPC: H01L23/31 ,  B29C67/00 ,  H01L21/56 ,  B29C70/72 ,  B33Y80/00 ,  B33Y40/00 ,  B81C1/00 ,  H01L21/48 ,  B29K25/00 ,  B29K33/04 ,  B29K105/00 ,  B29L31/34

CPC classification number: H01L23/3135 ,  B29C64/00 ,  B29C64/10 ,  B29C64/106 ,  B29C70/72 ,  B29K2025/08 ,  B29K2033/04 ,  B29K2105/253 ,  B29L2031/3481 ,  B33Y40/00 ,  B33Y80/00 ,  B81C1/00309 ,  B81C2203/0136 ,  H01L21/4867 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/315 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: In one aspect, a method of packaging a semiconductor module includes providing a semiconductor module having a first surface, a second surface opposite the first surface and edge sides extending between the first surface and the second surface. A packaging assembly is formed at least partly by a 3D printing process. The packaging assembly includes the semiconductor module and a protective covering that extends over the first surface.

公开(公告)号：US09780061B2

公开(公告)日：2017-10-03

申请号：US14287080

申请日：2014-05-26

Applicant: Infineon Technologies AG

Inventor： Franz Gabler ,  Horst Theuss

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49524 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8392 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer at least on portions of the electronic chip; and molding an encapsulation which covers the electronic chip and the supporting structure at least partially by using a molding material comprising a matrix material and a conductive filler material.

公开(公告)号：US20170275159A1

公开(公告)日：2017-09-28

申请号：US15079593

申请日：2016-03-24

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Kok Yau Chua ,  Swee Kah Lee ,  Chee Yang Ng ,  Horst Theuss

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/552

CPC classification number: B81C1/00333 ,  B81B7/0064 ,  B81C2203/019 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4878 ,  H01L23/10 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861 ,  H01L23/552

Abstract: A base plate with a first side having an elevated portion, a recessed portion laterally surrounding the elevated portion, and a vertical face extending from the recessed portion to the elevated portion is provided. At least a part of the vertical face is covered with a metal layer. A mold compound structure is formed on the first side with the metal layer disposed between the first side and the mold compound structure such that the mold compound structure includes an elevated portion laterally surrounding a recessed portion, and opposing edge faces that vertically extend from the recessed portion to the elevated portion. At least a part of the base plate is subsequently removed such that the recessed portion of the mold compound structure is uncovered from the base plate and such that the metal layer remains on at least one uncovered section of the mold compound structure.

公开(公告)号：US20170212036A1

公开(公告)日：2017-07-27

申请号：US15349438

申请日：2016-11-11

Applicant: Infineon Technologies AG

Inventor： Thomas Mueller ,  Horst Theuss ,  Klaus Elian ,  Rainer Markus Schaller ,  Stefan Kolb

IPC: G01N21/17

CPC classification number: G01N21/1702 ,  A61B5/0095 ,  A61B2562/0204 ,  G01N29/032 ,  G01N29/222 ,  G01N29/2418 ,  G01N29/48 ,  G01N33/0009 ,  G01N2021/1704 ,  G01N2291/021 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: A photo-acoustic gas sensor is disclosed. The photo-acoustic gas sensor includes a substrate, a light emitter unit supported by the substrate, the light emitter unit including a light emitter configured to emit a beam of light pulses with a predetermined repetition frequency and wavelength corresponding to an absorption band of a gas to be sensed, and a detector unit supported by the substrate, the detector unit including a microphone, wherein the beam of light pulses traverses an area intended to accommodate the gas and the microphone can receive a signal oscillating with the repetition frequency.

公开(公告)号：US09653405B2

公开(公告)日：2017-05-16

申请号：US13771222

申请日：2013-02-20

Applicant: Infineon Technologies AG

Inventor： Horst Theuss ,  Beng Keh See

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L24/85 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012

Abstract: In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.

公开(公告)号：US09593009B2

公开(公告)日：2017-03-14

申请号：US14515304

申请日：2014-10-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Horst Theuss ,  Rainer Leuschner

IPC: B81B7/00 ,  H04R19/00 ,  H04R31/00 ,  B81C1/00 ,  B81B3/00 ,  H01L23/00

CPC classification number: B81B7/0041 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00253 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H04R19/005 ,  H04R31/006 ,  H04R2201/003 ,  H01L2924/00

Abstract: A system and a method for forming a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device includes a MEMS device having a first main surface with a first area along a first direction and a second direction, a membrane disposed on the first main surface of the MEMS device and a backplate adjacent to the membrane. The packaged MEMS device further includes an encapsulation material that encapsulates the MEMS device and that defines a back volume, the back volume having a second area along the first direction and the second direction, wherein the first area is smaller than the second area.

Abstract translation: 公开了一种用于形成封装的MEMS器件的系统和方法。 在一个实施例中，封装的MEMS器件包括具有第一主表面的MEMS器件，第一主表面具有沿着第一方向的第一区域和第二方向，设置在MEMS器件的第一主表面上的膜和邻近膜的背板。 封装的MEMS器件还包括封装MEMS器件并且限定后部体积的封装材料，后部体积具有沿第一方向和第二方向的第二区域，其中第一区域小于第二区域。

公开(公告)号：US20170057815A1

公开(公告)日：2017-03-02

申请号：US14833871

申请日：2015-08-24

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Horst Theuss

IPC: B81C1/00 ,  B81B7/00 ,  H01L21/56

CPC classification number: H01L21/563 ,  B81B7/0038 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00285 ,  B81C2203/0118 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A first semiconductor substrate having at least one integrated semiconductor device is provided. A lift-off layer is formed on a main surface of the first semiconductor substrate. The lift-off layer is patterned so as to form openings in the lift-off layer that are arranged on either side of a first portion of the lift-off layer. The first substrate is connected together with a second substrate by an interconnect structure to form an assembly with the main surface of the first semiconductor substrate being exposed. Exposed surfaces of the assembly are coated with a parylene coating, with a first portion of the parylene coating being supported by the first portion of the lift-off layer. The first portion of the parylene coating is selectively removed using a lift-off technique that removes the first portion of the lift-off layer. The lift-off technique is performed after connecting the first substrate and second substrates together.

Abstract translation: 提供具有至少一个集成半导体器件的第一半导体衬底。 在第一半导体衬底的主表面上形成剥离层。 剥离层被图案化以在剥离层中形成布置在剥离层的第一部分的任一侧上的开口。 第一衬底通过互连结构与第二衬底连接在一起，以形成暴露第一半导体衬底的主表面的组件。 组件的暴露表面涂覆有聚对二甲苯涂层，聚对二甲苯涂层的第一部分由剥离层的第一部分支撑。 使用去除剥离层的第一部分的剥离技术选择性地除去聚对二甲苯涂层的第一部分。 在将第一基板和第二基板连接在一起之后进行剥离技术。