公开(公告)号：US20160126149A1

公开(公告)日：2016-05-05

申请号：US14527811

申请日：2014-10-30

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler ,  Erich Griebl ,  Manfred Pirker ,  Andreas Moser

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L22/14 ,  H01L21/28158 ,  H01L22/34 ,  H01L29/66568 ,  H01L29/94

Abstract: According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.

Abstract translation: 根据各种实施例，用于处理衬底的方法可以包括：在衬底上形成电介质层，电介质层可以包括多个测试区域; 在所述电介质层上形成导电层以接触所述多个测试区域中的介电层; 同时对多个测试区域中的电介质层进行电学检查，其中与多个测试区域中的电介质层接触的导电层的部分通过导电材料彼此导电连接; 以及将所述导电层分离成所述多个测试区域中与所述电介质层接触的所述导电层的部分。

公开(公告)号：US20150348921A1

公开(公告)日：2015-12-03

申请号：US14290448

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Abstract translation: 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US09142444B2

公开(公告)日：2015-09-22

申请号：US13895132

申请日：2013-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Markus Zundel ,  Erwin Bacher ,  Andreas Behrendt ,  Joerg Ortner ,  Walter Rieger ,  Rudolf Zelsacher

IPC: H01L21/8242 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/861

CPC classification number: H01L21/76224 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.

Abstract translation: 半导体部件包括在半导体主体中具有至少一个保护沟槽的半导体本体。 绝缘层至少位于保护沟槽的底部。 在保护沟槽中的绝缘层上形成具有厚度D的导电层，其中导电层仅部分地填充保护沟槽。