公开(公告)号：US11239188B2

公开(公告)日：2022-02-01

申请号：US15817810

申请日：2017-11-20

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Rainer Pelzer ,  Manfred Schneegans

IPC: H01L23/00

Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

公开(公告)号：US20210265497A1

公开(公告)日：2021-08-26

申请号：US17316067

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

公开(公告)号：US10672661B2

公开(公告)日：2020-06-02

申请号：US16176403

申请日：2018-10-31

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Stefan Mieslinger ,  Thomas Ostermann ,  Christian Westermeier ,  Jochen Hilsenbeck ,  Jens Peter Konrath ,  Boris Mayerhofer ,  Anatoly Sotnikov

IPC: H01L21/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.

公开(公告)号：US10453915B2

公开(公告)日：2019-10-22

申请号：US15941637

申请日：2018-03-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Karl-Heinz Bach ,  Christian Kampen ,  Dietmar Kotz ,  Andrew Christopher Graeme Wood ,  Markus Zundel

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265

Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.

公开(公告)号：US10217830B2

公开(公告)日：2019-02-26

申请号：US15373128

申请日：2016-12-08

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Thomas Ostermann ,  Michael Sorger

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region. The electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and an electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.

公开(公告)号：US10115817B2

公开(公告)日：2018-10-30

申请号：US15157645

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Peter Brandl

IPC: H01L29/745 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.

公开(公告)号：US09966277B2

公开(公告)日：2018-05-08

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

公开(公告)号：US09941403B2

公开(公告)日：2018-04-10

申请号：US13627215

申请日：2012-09-26

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Markus Zundel

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/7813 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0883 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7828

Abstract: A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench.

公开(公告)号：US20170194417A1

公开(公告)日：2017-07-06

申请号：US15465715

申请日：2017-03-22

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Thomas Gross ,  Werner Irlbacher ,  Markus Zundel ,  Mathias von Borcke ,  Hans Joachim Schulze

IPC: H01L49/02 ,  H01L21/266

CPC classification number: H01L28/20 ,  G01K7/186 ,  H01L21/266 ,  H01L27/0802

Abstract: A method for producing a polysilicon resistor device may include: forming a polysilicon layer; implanting first dopant atoms into at least a portion of the polysilicon layer, wherein the first dopant atoms include deep energy level donors; implanting second dopant atoms into said at least a portion of said polysilicon layer; and annealing said at least a portion of said polysilicon layer.

公开(公告)号：US09559167B2

公开(公告)日：2017-01-31

申请号：US15004467

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler

IPC: H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861

Abstract: One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches.

Abstract translation: 一个实施例提供了包括具有第一侧和第二侧以及漂移区的半导体本体的半导体部件; 与所述漂移区域互补地并且在所述第一侧的方向上与所述漂移区域相邻地掺杂的第一半导体区域; 与所述漂移区相邻的所述漂移区与所述第二侧方向相同的导电类型的第二半导体区; 至少两个沟槽布置在半导体本体中并延伸到半导体本体中并且彼此间隔一定距离; 以及设置在与漂移区相邻的至少两个沟槽中的场电极。 所述至少两个沟槽在垂直方向上与所述第二半导体区域一定距离地布置，所述沟槽和所述第二半导体区域之间的距离大于所述沟槽之间的相互距离的1.5倍，并且所述漂移区域的掺杂浓度 在沟槽和第二半导体区域之间的区段中，在沟槽之间的截面中与最小掺杂浓度相差至多35％。