公开(公告)号：US20240055531A1

公开(公告)日：2024-02-15

申请号：US18494384

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L29/78648 ,  H01L29/0847 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/78696 ,  H01L29/1037 ,  H01L21/02647 ,  H01L29/6656 ,  H01L29/42384 ,  H10B12/05 ,  H10B12/50 ,  H10B12/315 ,  H01L21/31116

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US20230420363A1

公开(公告)日：2023-12-28

申请号：US18314875

申请日：2023-05-10

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Elliot Tan ,  Abhishek A. Sharma ,  Shem Odhiambo Ogadhoh ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L23/528 ,  H01L27/092

CPC classification number: H01L23/528 ,  H01L27/0924

Abstract: IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

公开(公告)号：US20230413547A1

公开(公告)日：2023-12-21

申请号：US17843867

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

IPC: H01L27/1156 ,  H01L27/11524

CPC classification number: H01L27/1156 ,  H01L27/11524

Abstract: IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

公开(公告)号：US11832438B2

公开(公告)日：2023-11-28

申请号：US16457634

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Jared Stoeger ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00 ,  H01L27/12 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L28/82 ,  H10B12/0335 ,  H10B12/312

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20230307291A1

公开(公告)日：2023-09-28

申请号：US17656366

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Moshe Dolejsi ,  Harish Ganapathy ,  Travis W. Lajoie ,  Deepyanti Taneja ,  Huiying Liu ,  Cheng Tan ,  Timothy Jen ,  Van H. Le ,  Abhishek A. Sharma

IPC: H01L21/768 ,  H01L27/108 ,  H01L23/522

CPC classification number: H01L21/76829 ,  H01L21/76859 ,  H01L23/5226 ,  H01L27/10852

Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

公开(公告)号：US11764303B2

公开(公告)日：2023-09-19

申请号：US16957617

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78672 ,  H01L2029/42388

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US20230290831A1

公开(公告)日：2023-09-14

申请号：US17690358

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Ravi Pillarisetty ,  Willy Rachmady ,  Sagar Suthram ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/1033 ,  H01L29/45 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/401 ,  H01L27/10826

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Reducing transistor dimensions at the gate allows keeping the footprint of the transistor relatively small and comparable to what could be achieved implementing a transistor with a shorter gate length while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower.

公开(公告)号：US11758711B2

公开(公告)日：2023-09-12

申请号：US17696945

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-Hua Wang ,  Chieh-Jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00 ,  H01L27/06 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L23/528 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0605 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US11742429B2

公开(公告)日：2023-08-29

申请号：US17508843

申请日：2021-10-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Li Huey Tan ,  Tristan A. Tronic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78681 ,  H01L29/0669 ,  H01L29/20 ,  H01L29/42384 ,  H01L29/66742

Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.