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公开(公告)号：US20160357614A1
公开(公告)日：2016-12-08
申请号：US14729914
申请日：2015-06-03
Applicant: Intel Corporation
Inventor： Shou C. Chen , Andreas Kleen
IPC: G06F9/52
CPC classification number: G06F9/528 , G06F9/467 , G06F9/48 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/52 , G06F9/526
Abstract: Adaptive queued locking for control of speculative execution is disclosed. An example apparatus includes a lock to: enforce a first quota to control a number of threads allowed to concurrently speculatively execute after being placed in a queue; and in response to the first quota not having been reached, enable a first thread from the queue to speculatively execute; and an adjuster to change a first value of the first quota based on a result of the speculative execution of the first thread.
Abstract translation: 公开了用于控制推测执行的自适应排队锁定。 一种示例性装置包括：用于：强制执行第一配额以控制在被放置在队列中之后允许同时推测地执行的多个线程的锁; 并且响应于未达到的第一配额，使队列中的第一个线程推测地执行; 以及调整器，其基于所述第一线程的推测性执行的结果来改变所述第一配额的第一值。
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12.发明公开公开(公告)号：US20240111539A1
公开(公告)日：2024-04-04
申请号：US17957969
申请日：2022-09-30
Applicant: Intel Corporation
Inventor： Jason Agron , Andreas Kleen , Rangeen Basu Roy Chowdhury
CPC classification number: G06F9/3802 , G06F9/30189
Abstract: Techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. In an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. Based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. The page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. Based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. In another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.
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公开(公告)号：US20240103868A1
公开(公告)日：2024-03-28
申请号：US17953486
申请日：2022-09-27
Applicant: Intel Corporation
Inventor： Andreas Kleen , Jason W. Brandt , Gilbert Neiger , Ittai Anati
CPC classification number: G06F9/3016 , G06F9/30065 , G06F9/45558 , G06F2009/45591
Abstract: Techniques relating to virtual idle loops are described. In an embodiment, decoder circuitry decodes a single instruction. The single instruction includes a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode. Execution circuitry executes the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20230315470A1
公开(公告)日：2023-10-05
申请号：US17708933
申请日：2022-03-30
Applicant: Intel Corporation
Inventor： Matthew Merten , Beeman Strong , Moshe Cohen , Ahmad Yasin , Andreas Kleen , Stanislav Bratanov , Karthik Gopalakrishnan , Angela Schmid , Grant Zhou
CPC classification number: G06F9/3814 , G06F9/30101 , G06F9/321 , G06F11/3409
Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.
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公开(公告)号：US11526440B2
公开(公告)日：2022-12-13
申请号：US16433671
申请日：2019-06-06
Applicant: Intel Corporation
Inventor： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20200210178A1
公开(公告)日：2020-07-02
申请号：US16811242
申请日：2020-03-06
Applicant: Intel Corporation
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
IPC: G06F9/30
Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.
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公开(公告)号：US20200004677A1
公开(公告)日：2020-01-02
申请号：US16020444
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Amin Firoozshahian , Omid Azizi , Chandan Egbert , David Hansen , Andreas Kleen , Mahesh Maddury , Mahesh Madhav , Alexandre Solomatnikov , John Peter Stevenson
IPC: G06F12/02 , G06F12/1009 , G06F3/06
Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.
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公开(公告)号：US10191784B2
公开(公告)日：2019-01-29
申请号：US15631913
申请日：2017-06-23
Applicant: Intel Corporation
Inventor： Shou C. Chen , Andreas Kleen
Abstract: Adaptive queued locking for control of speculative execution is disclosed. An example apparatus includes a queue controller to control removal of threads from a queue that contains threads waiting to be permitted to speculatively execute in a critical section of a multi-threaded program. The apparatus also includes a first thread associated with a head node of the queue. The queue controller controls the removal of threads from the queue in response to operations performed by the first thread. In addition, an adjuster to change a number of threads permitted to speculatively execute based on a rate of threads currently speculatively executing transactions in the critical section is included.
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公开(公告)号：US09965375B2
公开(公告)日：2018-05-08
申请号：US15194881
申请日：2016-06-28
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
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公开(公告)号：US11681611B2
公开(公告)日：2023-06-20
申请号：US17119679
申请日：2020-12-11
Applicant: Intel Corporation
Inventor： Omid Azizi , Amin Firoozshahian , Andreas Kleen , Mahesh Madhav , Mahesh Maddury , Chandan Egbert , Eric Gouldey
CPC classification number: G06F12/0246 , G06F3/0604 , G06F3/065 , G06F3/0608 , G06F3/0641 , G06F9/5016 , G06F12/0292
Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.
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