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公开(公告)号：US12288072B2
公开(公告)日：2025-04-29
申请号：US17214823
申请日：2021-03-27
Applicant: Intel Corporation
Inventor： Jonathan Combs , Michael Chynoweth , Beeman Strong , Charlie Hewett , Patrick Konsor , Vidisha Chirra , Asavari Paranjape , Ahmad Yasin
IPC: G06F11/34 , G06F9/38 , G06F11/30 , G06F12/0802 , G06F17/40
Abstract: Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.
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公开(公告)号：US12282778B2
公开(公告)日：2025-04-22
申请号：US18479974
申请日：2023-10-03
Applicant: Intel Corporation
Inventor： Jared W. Stark , Ahmad Yasin , Ajay Amarsingh Singh
IPC: G06F9/38 , G06F9/30 , G06F12/0804
Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.
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公开(公告)号：US11915000B2
公开(公告)日：2024-02-27
申请号：US18160600
申请日：2023-01-27
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Raanan Sade , Liron Zur , Igor Yanover , Joseph Nuzman
CPC classification number: G06F9/30145 , G06F9/30098 , G06F9/544 , G06F9/546 , G06F11/3037 , G06F11/348
Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.
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公开(公告)号：US20230092268A1
公开(公告)日：2023-03-23
申请号：US17992407
申请日：2022-11-22
Applicant: Intel Corporation
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
IPC: G06F9/30
Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.
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公开(公告)号：US20220261246A1
公开(公告)日：2022-08-18
申请号：US17675962
申请日：2022-02-18
Applicant: Intel Corporation
Inventor： Ahmad Yasin
Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20210200656A1
公开(公告)日：2021-07-01
申请号：US16728617
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： ELIEZER WEISSMANN , Omer Barak , Rajshree Chabukswar , Russell Fenger , Eugene Gorbatov , Monica Gupta , Julius Mandelblat , Nir Misgav , Efraim Rotem , Ahmad Yasin
Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.
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公开(公告)号：US20210200580A1
公开(公告)日：2021-07-01
申请号：US16729370
申请日：2019-12-28
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Julius Mandelblat , Eliezer Weissmann , Rajshree A. Chabukswar , Michael W. Chynoweth
Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.
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公开(公告)号：US10997048B2
公开(公告)日：2021-05-04
申请号：US15395903
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： Ahmad Yasin
Abstract: An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.
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公开(公告)号：US20200319883A1
公开(公告)日：2020-10-08
申请号：US16831007
申请日：2020-03-26
Applicant: INTEL CORPORATION
Inventor： Ahmad Yasin
Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.
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公开(公告)号：US20180217839A1
公开(公告)日：2018-08-02
申请号：US15423143
申请日：2017-02-02
Applicant: INTEL CORPORATION
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
CPC classification number: G06F9/3005
Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.
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