公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20190019691A1

公开(公告)日：2019-01-17

申请号：US16071826

申请日：2016-02-26

Applicant: INTEL CORPORATION

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/498

Abstract: Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20250125277A1

公开(公告)日：2025-04-17

申请号：US19000025

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sri Ranga Sai BOYAPATI ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Javier SOTO GONZALEZ ,  Kwangmo LIM

IPC: H01L23/538 ,  H01L23/00

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US20250118647A1

公开(公告)日：2025-04-10

申请号：US18988225

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US20240332195A1

公开(公告)日：2024-10-03

申请号：US18129879

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Naiya SOETAN-DODD ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Brandon C. MARIN ,  Sheng C. LI ,  Liwei CHENG

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16235

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a cavity is in the core, and a bridge is in the cavity. In an embodiment, the bridge comprises through substrate vias (TSVs). In an embodiment, pads are at a bottom of the cavity, where the TSVs are electrically coupled to the pads.

公开(公告)号：US20240213328A1

公开(公告)日：2024-06-27

申请号：US18089494

申请日：2022-12-27

Applicant: INTEL CORPORATION

Inventor： Vinith BEJUGAM ,  Yonggang LI ,  Srinivas V. PIETAMBARAM ,  Chandrasekharan NAIR ,  Whitney BRYKS ,  Gene CORYELL

IPC: H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L29/1606 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/16 ,  H01L2924/15311

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.

公开(公告)号：US20240213164A1

公开(公告)日：2024-06-27

申请号：US18089483

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Gang DUAN ,  Liang HE ,  Ziyin LIN ,  Elizabeth NOFEN ,  Yiqun BAI ,  Jonathan ATKINS ,  Jesus S. NIETO PESCADOR ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5381 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/14 ,  H01L2224/16104

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. In an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. In an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. In an embodiment, a non-conductive film (NCF) is around the solder between the first pads and the second pads.

公开(公告)号：US20240071935A1

公开(公告)日：2024-02-29

申请号：US17895965

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/80894 ,  H01L2224/80895

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.