中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

46 records (took 0.024 seconds)

    INTEGRATED CIRCUIT DEVICES WITH FRONT-END METAL STRUCTURES
    12.
    发明申请
    INTEGRATED CIRCUIT DEVICES WITH FRONT-END METAL STRUCTURES 审中-公开

    公开(公告)号：US20190393130A1

    公开(公告)日：2019-12-26

    申请号：US16018268

    申请日：2018-06-26

    Applicant: Intel IP Corporation

    Inventor： Reinhard Mahnkopf ,  Sonja Koller ,  Andreas Wolter

    IPC: H01L23/373 ,  H01L27/12 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768

    Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

    Interconnect structure for a microelectronic device
    15.
    发明授权
    Interconnect structure for a microelectronic device 有权

    公开(公告)号：US10366968B2

    公开(公告)日：2019-07-30

    申请号：US15282855

    申请日：2016-09-30

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

    Vertical inductor for WLCSP
    16.
    发明授权
    Vertical inductor for WLCSP 有权

    公开(公告)号：US10290412B2

    公开(公告)日：2019-05-14

    申请号：US15036786

    申请日：2015-06-25

    Applicant: Intel IP Corporation

    Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

    IPC: H01L23/64 ,  H01F17/00 ,  H01F41/04 ,  H01F27/28

    Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

    ELECTRONIC PACKAGE WITH COIL FORMED ON CORE
    18.
    发明申请
    ELECTRONIC PACKAGE WITH COIL FORMED ON CORE 有权

    公开(公告)号：US20170162314A1

    公开(公告)日：2017-06-08

    申请号：US14956859

    申请日：2015-12-02

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

    IPC: H01F27/28 ,  H01F27/24

    CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

    Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

Patent Agency Ranking