公开(公告)号：US20210273342A1

公开(公告)日：2021-09-02

申请号：US17323278

申请日：2021-05-18

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01Q1/48

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US11031699B2

公开(公告)日：2021-06-08

申请号：US15892632

申请日：2018-02-09

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01Q1/48

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US20190304922A1

公开(公告)日：2019-10-03

申请号：US15937542

申请日：2018-03-27

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Thomas Ort ,  Andreas Wolter ,  Andreas Augustin ,  Veronica Sciriha ,  Bernd Waidhas

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/64

Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

公开(公告)号：US20210104359A1

公开(公告)日：2021-04-08

申请号：US17122351

申请日：2020-12-15

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC: H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F27/28

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

公开(公告)号：US20190279899A1

公开(公告)日：2019-09-12

申请号：US15917032

申请日：2018-03-09

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Shankar Chandrasekaran Jayendra ,  Shidlingeshwar Khatakalle

IPC: H01L21/768 ,  H01L49/02 ,  H01L21/3205

Abstract: Various embodiments include, for example, a noise suppression filter for a power-delivery network (PDN). In one exemplary embodiment, a capacitor device, which may be used as at least a portion of the noise suppression filter, includes a first conductive plate and a second conductive plate with a dielectric material formed between the first conductive plate and the second conductive plate. A floating conductive fill layer is formed within the dielectric material and between the first conductive plate and the second conductive plate. Other embodiments of capacitors, and methods of forming the capacitor, are disclosed.

公开(公告)号：US10896780B2

公开(公告)日：2021-01-19

申请号：US15910820

申请日：2018-03-02

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Andreas Augustin ,  Andreas Wolter

IPC: H01F27/40 ,  H01G4/30 ,  H01G4/005 ,  H01G4/40 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F27/28 ,  H01L23/532 ,  H03B5/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/768

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

公开(公告)号：US20160284461A1

公开(公告)日：2016-09-29

申请号：US14672162

申请日：2015-03-28

Applicant: INTEL IP CORPORATION

Inventor： Saravana Maruthamuthu

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F19/04 ,  H01F41/041 ,  H01F41/045 ,  H01F2027/2819 ,  H01L23/5227 ,  H01L28/10

Abstract: An apparatus including a device including a primary winding and a secondary winding interwound and magnetically coupled in two metal layers, wherein an inductance of one of the primary winding and the secondary winding is tuned for a target inductance ratio between the primary winding and the secondary winding. A method including forming an impedance matched transformer device on a substrate including a primary winding and a secondary winding interwound and magnetically coupled in two metal layers in a laterally coupled layout, wherein an inductance of one of the primary winding and the secondary winding is tuned for a target inductance ratio between the primary winding and the secondary winding.

Abstract translation: 一种包括初级绕组和次级绕组的装置，包括绕组和磁耦合在两个金属层中，其中初级绕组和次级绕组中的一个的电感被调谐以用于初级绕组和次级绕组之间的目标电感比 。 一种方法，包括在包括初级绕组和次级绕组的基板上形成阻抗匹配变压器装置，所述初级绕组和次级绕组在横向耦合的布局中以两个金属层相互缠绕并磁耦合，其中初级绕组和次级绕组中的一个的电感被调谐 初级绕组和次级绕组之间的目标电感比。

公开(公告)号：US08779564B1

公开(公告)日：2014-07-15

申请号：US13803143

申请日：2013-03-14

Applicant: Intel IP Corporation

Inventor： Mikael Knudsen ,  Thorsten Meyer ,  Saravana Maruthamuthu ,  Andreas Wolter ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01L23/552 ,  H01L27/06

CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/48 ,  H01L23/66 ,  H01L24/19 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0414 ,  H01Q9/0421 ,  H01Q23/00 ,  H01L2924/00

Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.

Abstract translation: 半导体器件可以包括：芯片; 芯片封装结构至少部分地围绕芯片并且具有被配置为接收第一电容耦合结构的接收区域; 设置在所述接收区域中的第一电容耦合结构; 以及设置在所述第一电容耦合结构上并且电容耦合到所述第一电容耦合结构的第二电容耦合结构。