公开(公告)号：US20180239391A1

公开(公告)日：2018-08-23

申请号：US15439190

申请日：2017-02-22

Applicant: Integrated Device Technology, Inc.

Inventor： David Chang ,  Xudong Shi ,  Shubing Zhai ,  Chenxiao Ren

IPC: G06F1/10 ,  G11C7/10

CPC classification number: G06F1/10 ,  G06F13/1689 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222

Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.