公开(公告)号：US10241538B2

公开(公告)日：2019-03-26

申请号：US15439190

申请日：2017-02-22

Applicant: Integrated Device Technology, Inc.

Inventor： David Chang ,  Xudong Shi ,  Shubing Zhai ,  Chenxiao Ren

IPC: G06F1/12 ,  G06F1/10 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  G06F13/16

Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

公开(公告)号：US20210124705A1

公开(公告)日：2021-04-29

申请号：US16667194

申请日：2019-10-29

Applicant: Integrated Device Technology, Inc.

Inventor： Shubing Zhai ,  Changxi Xu

IPC: G06F13/40 ,  G11C16/04

Abstract: An apparatus including a front port, a plurality of back ports and a plurality of switches. The front port may be configured to send/receive data to/from a controller. The plurality of back ports may each be configured to send/receive the data to/from one of a plurality of logical units of a memory. The plurality of switches may each be configured to connect the front port to one of the back ports in response to an input. The input may be received from the controller and may also be presented to the memory.

公开(公告)号：US20180275714A1

公开(公告)日：2018-09-27

申请号：US15468310

申请日：2017-03-24

Applicant: Integrated Device Technology, Inc.

Inventor： David Chang ,  Xudong Shi ,  Shubing Zhai ,  Chenxiao Ren

IPC: G06F1/12 ,  G06F13/42 ,  G06F1/10 ,  G06F13/40

CPC classification number: G06F13/4072 ,  G06F13/1689 ,  G06F13/4291

Abstract: An apparatus comprising an input interface an output interface and a coupling interface. The input interface may comprise a plurality of input stages each configured to (i) receive a data signal and a coupled clock signal and (ii) present an intermediate signal. The output interface may comprise a plurality of output stages each configured to (i) receive the intermediate signal from one of the input stages, (ii) receive the coupled clock signal and (iii) present an output signal. The coupling interface may be configured to (i) receive the clock signal and (ii) present the coupled clock signal to each of (a) the input stages and (b) the output stages. The coupling interface may generate a plurality of inductive couples and (b) the inductive couples may enable a synchronization of the coupled clock signal with the clock signal for each of the input stages and the output stages.

公开(公告)号：US20180239391A1

公开(公告)日：2018-08-23

申请号：US15439190

申请日：2017-02-22

Applicant: Integrated Device Technology, Inc.

Inventor： David Chang ,  Xudong Shi ,  Shubing Zhai ,  Chenxiao Ren

IPC: G06F1/10 ,  G11C7/10

CPC classification number: G06F1/10 ,  G06F13/1689 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222

Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.