公开(公告)号：US10559744B2

公开(公告)日：2020-02-11

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian Maertz ,  Christopher J. Wiegand ,  Daniel G. Oeullette ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Justin S. Brockman ,  Tahir Ghani ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Kaan Oguz

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US10079266B2

公开(公告)日：2018-09-18

申请号：US15122129

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Anant H. Jahagirdar ,  Mengcheng Lu

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

公开(公告)号：US10804460B2

公开(公告)日：2020-10-13

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani ,  Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US10732217B2

公开(公告)日：2020-08-04

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Kevin P. O'Brien ,  Kaan Oguz ,  Christopher J. Wiegand ,  Mark L. Doczy ,  Brian S. Doyle ,  MD Tofizur Rahman ,  Oleg Golonzka ,  Tahir Ghani

IPC: G01R31/28 ,  H01L43/12 ,  G01R33/09 ,  G01R31/315 ,  H01L21/66 ,  G01R33/60 ,  G01N24/10 ,  G01R35/00

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

公开(公告)号：US10651093B2

公开(公告)日：2020-05-12

申请号：US16020722

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/28

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US10340445B2

公开(公告)日：2019-07-02

申请号：US15755446

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/10 ,  H01F10/30 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

公开(公告)号：US10326075B2

公开(公告)日：2019-06-18

申请号：US15755437

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  G11C11/16

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US10256395B2

公开(公告)日：2019-04-09

申请号：US15735395

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Daniel R. Lamborn ,  Oleg Golonzka ,  Christopher J. Wiegand ,  Philip E. Heil ,  M D Tofizur Rahman ,  Rebecca J. Castellano ,  Tarun Bansal

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the sidewalls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.

公开(公告)号：US20190027536A1

公开(公告)日：2019-01-24

申请号：US15767127

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  Kaan Oguz ,  Kevin P. O'Brien ,  Tofizur Rahman ,  Brian S. Doyle ,  Tahir Ghani ,  Mark L. Doczy

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Disclosed herein are electrical contacts for magnetoresistive random access memory (MRAM) devices and related memory structures, devices, and methods. For example, and electrical contact for an MRAM device may include: a tantalum region; a barrier region formed of a first material; and a passivation region formed of a second material and disposed between the tantalum region and the barrier region, wherein the second material includes tantalum nitride and is different from the first material.

公开(公告)号：US20180182952A1

公开(公告)日：2018-06-28

申请号：US15735395

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Daniel R. Lamborn ,  Oleg Golonzka ,  Christopher J. Wiegand ,  Philip E. Heil ,  MD Tofizur Rahman ,  Rebecca J. Castellano ,  Tarun Bansal

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the side-walls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.