公开(公告)号：US20170288724A1

公开(公告)日：2017-10-05

申请号：US15088996

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Feras EID ,  Adel A. ELSHERBINI ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: H04B1/48 ,  H03H9/05 ,  H03H9/54 ,  H01H57/00

CPC classification number: H04B1/48 ,  H01H57/00 ,  H01H2057/006 ,  H03H7/38 ,  H03H2015/005

Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.

公开(公告)号：US20170287808A1

公开(公告)日：2017-10-05

申请号：US15625947

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Don W. NELSON

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L23/473

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

公开(公告)号：US20160211190A1

公开(公告)日：2016-07-21

申请号：US14914998

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Henning BRAUNISCH ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Don W. NELSON

IPC: H01L23/367 ,  H01L21/52 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

Abstract translation: 一种包括模具的设备，所述模具的第一侧包括第一类型的系统级接触点和包括第二类型的接触点的第二侧; 以及耦合到管芯和管芯的第二侧的封装衬底。 一种包括管芯的设备，所述管芯的第一侧包括多个系统级逻辑接触点和包括第二多个系统级电力接触点的第二侧。 一种方法，包括将管芯的第一侧上的第一类型的系统级接触点中的一个与管芯的第二侧上的第二类型的系统级接触点耦合到封装衬底。

公开(公告)号：US20240266745A1

公开(公告)日：2024-08-08

申请号：US18620275

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Feras EID ,  Sasha N. OSTER ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV

IPC: H01Q9/04 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/52 ,  H01Q19/22

CPC classification number: H01Q9/0414 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/241 ,  H01Q1/526 ,  H01Q19/22 ,  H01L23/3675 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

公开(公告)号：US20230344131A1

公开(公告)日：2023-10-26

申请号：US18216282

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Feras EID ,  Sasha N. OSTER ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV

IPC: H01Q9/04 ,  H01L23/31 ,  H01L23/495 ,  H01Q1/24 ,  H01Q19/22 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/66 ,  H01L21/56 ,  H01Q1/52

CPC classification number: H01Q9/0414 ,  H01L23/3107 ,  H01L23/49541 ,  H01Q1/241 ,  H01Q19/22 ,  H01Q1/2283 ,  H01L23/552 ,  H01L23/66 ,  H01L21/565 ,  H01Q1/526 ,  H01L2223/6677 ,  H01L23/3675

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

公开(公告)号：US20220415839A1

公开(公告)日：2022-12-29

申请号：US17357722

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Feras EID ,  Johanna M. SWAN ,  Adel A. ELSHERBINI ,  Shawna M. LIFF

IPC: H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

公开(公告)号：US20220301972A1

公开(公告)日：2022-09-22

申请号：US17834753

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Feras EID

IPC: H01L23/367 ,  H01L23/42

Abstract: A device package and a method of forming a device package are described. The device package includes a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface, where the lid is disposed on the substrate. The legs of the lid are attached to the substrate with a sealant. The device package also has one or more dies disposed on the substrate. The die(s) are below the bottom surface of the lid, where each of the dies has a top surface and a bottom surface. The device package further includes a retaining structure disposed between the bottom surface of the lid and the top surface of the die, where the retaining structure has one or more inner walls. The device package includes a thermal interface material disposed within the inner walls of the retaining structure and above the top surface of the die.

公开(公告)号：US20200064555A1

公开(公告)日：2020-02-27

申请号：US16072240

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. OSTER ,  Johanna M. SWAN ,  Feras EID ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Baris BICEN ,  Valluri R. RAO

IPC: G02B6/35 ,  H04Q11/00 ,  H04B10/25

Abstract: Embodiments of the invention include an optical routing device that includes an organic substrate. According to an embodiment, an array of cavities are formed into the organic substrate and an array of piezoelectrically actuated mirrors may be anchored to the organic substrate with each piezoelectrically actuated mirror extending over a cavity. In order to properly rout incoming optical signals, the optical routing device may also include a routing die mounted on the organic substrate. The routing die may be electrically coupled to each of the piezoelectrically actuated mirrors and is able to generated a voltage across the first and second electrodes of each piezoelectrically actuated mirror. Additionally, a photodetector may be electrically coupled to the routing die. According to an embodiment, an array of fiber optic cables may be optically coupled with one of the piezoelectrically actuated mirrors and optically coupled with the photodetector.

公开(公告)号：US20200051743A1

公开(公告)日：2020-02-13

申请号：US16606130

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Feras EID ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Kristof DARMAWIKARTA

IPC: H01G4/14 ,  H05K1/02 ,  H05K1/03

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes.

公开(公告)号：US20190252597A1

公开(公告)日：2019-08-15

申请号：US16397356

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Feras EID ,  Shawna M. LIFF

IPC: H01L41/053 ,  H01L41/047 ,  H01L41/23

CPC classification number: H01L41/0533 ,  H01L41/047 ,  H01L41/094 ,  H01L41/23 ,  H01L41/332 ,  H03H9/10

Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.