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公开(公告)号：US10592445B2
公开(公告)日：2020-03-17
申请号：US16208224
申请日：2018-12-03
Applicant: Intel Corporation
Inventor： Bill Nale , Christopher E. Cox , Kuljit S. Bains , George Vergis , James A. McCall , Chong J. Zhao , Suneeta Sah , Pete D. Vogt , John R. Goles
Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
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公开(公告)号：US20190288421A1
公开(公告)日：2019-09-19
申请号：US16431498
申请日：2019-06-04
Applicant: Intel Corporation
Inventor： Jong-Ru Guo , Yunhui Chu , Jun Liao , Kai Xiao , Jingbo Li , Yuanhong Zhao , Mo Liu , Beomtaek Lee , James A. McCall , Jaejin Lee , Xiaoning Ye , Zuoguo Wu , Xiang Li
Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.
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13.发明授权公开(公告)号：US10121528B2
公开(公告)日：2018-11-06
申请号：US14440068
申请日：2013-11-22
Applicant: Intel Corporation
Inventor： George Vergis , Kuljit S. Bains , James A. McCall , Ge Chang
IPC: G06F12/00 , G11C11/4074 , G06F3/06 , G11C7/10 , G11C8/06 , G06F13/16 , G11C11/408
Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.
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公开(公告)号：US20180226118A1
公开(公告)日：2018-08-09
申请号：US15944755
申请日：2018-04-03
Applicant: Intel Corporation
Inventor： Christopher P. Mozak , Randy B. Osborne , Michael Gutzmann , James A. McCall
IPC: G11C11/4093 , G11C11/4076 , G11C11/4096
CPC classification number: G11C11/4093 , G06F13/1684 , G06F13/1689 , G11C11/4076 , G11C11/4096
Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.
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15.发明申请公开(公告)号：US20170199830A1
公开(公告)日：2017-07-13
申请号：US15196014
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Bill Nale , Kuljit S. Bains , George Vergis , Christopher E. Cox , James A. McCall , Chong J. Zhao , Suneeta Sah , Pete D. Vogt , John R. Goles
IPC: G06F13/16 , G11C11/4096 , G06F13/40 , G11C14/00
CPC classification number: G06F13/1673 , G06F13/4068 , G11C5/04 , G11C7/10 , G11C7/1045 , G11C11/4096
Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
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Patent Agency Ranking
公开(公告)号：US09596766B2
公开(公告)日：2017-03-14
申请号：US14173554
申请日：2014-02-05
Applicant: Intel Corporation
Inventor： David N. Shykind , James A. McCall
CPC classification number: H05K3/10 , H05K1/0216 , H05K1/0245 , H05K1/0248 , H05K1/0366 , H05K3/0052 , H05K2201/0187 , H05K2201/029 , H05K2201/09236 , H05K2201/09972 , H05K2203/1554 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49798 , Y10T428/24058 , Y10T428/24917 , Y10T428/249935 , Y10T428/24994 , Y10T428/249943 , Y10T428/249946 , Y10T442/2926 , Y10T442/2992 , Y10T442/3065
Abstract: A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.
Abstract translation: 这里描述了制造电路板的方法。 该方法可以包括添加树脂，形成第一和第二玻璃纤维纤维，以及形成能够传输电信号的第一和第二信号线迹线。 在一些实例中，第一信号线迹线附近的玻璃纤维和树脂材料之间的比率类似于第二信号线迹线附近的玻璃纤维和树脂材料之间的比率。 在一些示例中，第一和第二玻璃纤维光纤在第一和第二信号线迹线附近对角地交叉。 在一些示例中，第一和第二玻璃纤维纤维以锯齿形图案在第一和第二信号线迹线附近交叉。
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公开(公告)号：US11074959B2
公开(公告)日：2021-07-27
申请号：US16741368
申请日：2020-01-13
Applicant: Intel Corporation
Inventor： James A. McCall , Christopher P. Mozak , Christopher E. Cox , Yan Fu , Robert J. Friar , Hsien-Pao Yang
IPC: G11C11/40 , G11C11/4072 , G06F3/06 , G11C7/10 , G11C11/4093 , G11C11/4076 , G06F13/16
Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
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公开(公告)号：US10467160B2
公开(公告)日：2019-11-05
申请号：US15719742
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Xiang Li , Yunhui Chu , Jun Liao , George Vergis , James A. McCall , Charles C. Phares , Konika Ganguly , Qin Li
Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
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公开(公告)号：US10033382B2
公开(公告)日：2018-07-24
申请号：US15423431
申请日：2017-02-02
Applicant: Intel Corporation
Inventor： James A. McCall , Kuljit S. Bains
IPC: H03K19/00 , G11C11/4093 , G11C11/4074
Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
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公开(公告)号：US20170255412A1
公开(公告)日：2017-09-07
申请号：US15200981
申请日：2016-07-01
Applicant: Intel Corporation
Inventor： Christopher E. Cox , Kuljit S. Bains , James A. McCall
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0604 , G06F3/0611 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C2207/2254
Abstract: Examples include techniques for command based on die termination (ODT). In some examples, values are programmed to registers at a memory device to establish one or more internal resistance termination (RTT) settings of ODT at the memory device. Values are also programmed to registers at the memory device to establish one more settings for timing of ODT latency. Programmed values may be changed in order to adjust a signal integrity for the memory device during read or write operations.
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