公开(公告)号：US10121528B2

公开(公告)日：2018-11-06

申请号：US14440068

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Ge Chang

IPC: G06F12/00 ,  G11C11/4074 ,  G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G06F13/16 ,  G11C11/408

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

公开(公告)号：US20190139592A1

公开(公告)日：2019-05-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Ge Chang

IPC: G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G06F3/06 ,  G06F13/16

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

公开(公告)号：US20150279444A1

公开(公告)日：2015-10-01

申请号：US14440068

申请日：2013-11-22

Applicant: George VERGIS ,  Kuljit S. BAINS ,  James A. MCCALL ,  Ge CHANG ,  INTEL CORPORATION

Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Ge Chang

IPC: G11C11/4074 ,  G11C7/10 ,  G06F13/16 ,  G11C11/408

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

Abstract translation: 用于为存储器件的多个芯片提供终端的技术和机制。 在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。 在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。 在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。 在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

公开(公告)号：US10943640B2

公开(公告)日：2021-03-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Ge Chang

IPC: G06F12/00 ,  G11C11/4074 ,  G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G06F13/16 ,  G11C11/408

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.