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    Apparatus and method for adaptively scheduling work on heterogeneous processing resources
    13.
    发明授权
    Apparatus and method for adaptively scheduling work on heterogeneous processing resources 有权

    公开(公告)号：US11436118B2

    公开(公告)日：2022-09-06

    申请号：US16728617

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Eliezer Weissmann ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

    IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F9/455 ,  G06F15/80

    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

    Restricting clock signal delivery in a processor
    16.
    发明授权
    Restricting clock signal delivery in a processor 有权
    限制处理器中的时钟信号传递

    公开(公告)号：US09471088B2

    公开(公告)日：2016-10-18

    申请号：US13925986

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Efraim Rotem ,  Julius Mandelblat ,  Alexander Lyakhov ,  Larisa Novakovsky ,  George Leifman ,  Lev Makovsky ,  Ariel Sabba ,  Niv Tokman

    IPC: G06F1/08 ,  G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/32

    Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑 的第一时钟信号发送到多个单元中的至少一个。 限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。 描述和要求保护其他实施例。

    ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION
    18.
    发明申请
    ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION 审中-公开

    公开(公告)号：US20190042157A1

    公开(公告)日：2019-02-07

    申请号：US16024637

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Julius Mandelblat ,  Nir Sucher

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

    Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

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