公开(公告)号：US11900115B2

公开(公告)日：2024-02-13

申请号：US18126920

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/30098 ,  G06F9/4812 ,  G06F9/5005 ,  G06F15/80

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US11048512B1

公开(公告)日：2021-06-29

申请号：US16833598

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/50 ,  G06F9/30 ,  G06F15/80 ,  G06F9/48

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US10990534B2

公开(公告)日：2021-04-27

申请号：US16264447

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Wei Chen ,  Eswaramoorthi Nallusamy ,  Larisa Novakovsky ,  Mark Schmisseur ,  Eric Rasmussen ,  Stephen Van Doren ,  Yen-Cheng Liu

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0802 ,  G06F12/02

Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

公开(公告)号：US10725848B2

公开(公告)日：2020-07-28

申请号：US15890893

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Ki W. Yoon ,  Michael J. St. Clair ,  Larisa Novakovsky ,  Hisham Shafi ,  William H. Penner ,  Yoni Aizik ,  Kevin Safford ,  Hermann Gartler

IPC: G06F11/00 ,  G06F11/07 ,  G06F9/38

Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

公开(公告)号：US10719326B2

公开(公告)日：2020-07-21

申请号：US15886313

申请日：2018-02-01

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Szapiro

IPC: G06F1/26 ,  G06F9/38 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.

公开(公告)号：US20170286304A1

公开(公告)日：2017-10-05

申请号：US15087917

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Leeor Peled ,  Joseph Nuzman ,  Larisa Novakovsky

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0897 ,  G06F2212/1024

Abstract: A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.

公开(公告)号：US09684595B2

公开(公告)日：2017-06-20

申请号：US15162707

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0871 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

公开(公告)号：US20140281239A1

公开(公告)日：2014-09-18

申请号：US13843315

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US20190102324A1

公开(公告)日：2019-04-04

申请号：US15721631

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Meltem Ozsoy ,  Krystof C. Zmudzinski ,  Larisa Novakovsky ,  Julius Mandelblat ,  Francis X. McKeen ,  Carlos V. Rozas ,  Ittai Anati ,  Ilya Alexandrovich

IPC: G06F12/14 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/0806 ,  G06F12/1027 ,  G06F12/0888 ,  G06F12/1009

Abstract: Cache behavior for secure memory repartitioning systems is described. Implementations may include a processing core and a memory controller coupled between the processor core and a memory device. The processor core is to receive a memory access request to a page in the memory device, the memory access request comprising a first guarded attribute (GA) indicator indicating whether the page is a secure page belonging to an enclave, determine whether the first GA indicator matches a second GA indicator in a cache line entry corresponding to the page, the cache line entry comprised in a cache, and responsive to a determination that the first GA indicator does not match the second GA indicator, apply an eviction policy to the cache line entry based on whether the cache line is indicated as a dirty cache line and accessing second data in the memory device for the page.

公开(公告)号：US10175992B2

公开(公告)日：2019-01-08

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F9/44 ,  G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.