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公开(公告)号:US20240356868A1
公开(公告)日:2024-10-24
申请号:US18761834
申请日:2024-07-02
Applicant: Intel Corporation
Inventor: Kevin Safford , Victor Ruybalid
CPC classification number: H04L49/109 , G06F13/42 , H04L12/44 , H04L45/02 , H04L45/16 , H04L45/48 , G06F2213/0038
Abstract: Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.
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2.
公开(公告)号:US08886979B2
公开(公告)日:2014-11-11
申请号:US13913864
申请日:2013-06-10
Applicant: Intel Corporation
Inventor: Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
CPC classification number: G06F1/3234 , G06F1/3203
Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
Abstract translation: 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型,基于指令的类型在执行周期中计算功耗,并将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑,用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器,以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。
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公开(公告)号:US12034649B2
公开(公告)日:2024-07-09
申请号:US16876902
申请日:2020-05-18
Applicant: Intel Corporation
Inventor: Kevin Safford , Victor Ruybalid
CPC classification number: H04L49/109 , G06F13/42 , H04L12/44 , H04L45/02 , H04L45/16 , H04L45/48 , G06F2213/0038
Abstract: Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.
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公开(公告)号:US10725848B2
公开(公告)日:2020-07-28
申请号:US15890893
申请日:2018-02-07
Applicant: Intel Corporation
Inventor: Tsvika Kurts , Ki W. Yoon , Michael J. St. Clair , Larisa Novakovsky , Hisham Shafi , William H. Penner , Yoni Aizik , Kevin Safford , Hermann Gartler
Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.
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公开(公告)号:US20200280526A1
公开(公告)日:2020-09-03
申请号:US16876902
申请日:2020-05-18
Applicant: Intel Corporation
Inventor: Kevin Safford , Victor Ruybalid
IPC: H04L12/933 , H04L12/761 , H04L12/753 , H04L12/751 , H04L12/44 , G06F13/42
Abstract: Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.
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公开(公告)号:US20190243701A1
公开(公告)日:2019-08-08
申请号:US15890893
申请日:2018-02-07
Applicant: Intel Corporation
Inventor: Tsvika Kurts , Ki W. Yoon , Michael J. St. Clair , Larisa Novakovsky , Hisham Shafi , William H. Penner , Yoni Aizik , Kevin Safford , Hermann Gartler
Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.
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