公开(公告)号：US11776898B2

公开(公告)日：2023-10-03

申请号：US16955722

申请日：2018-02-22

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Anh Phan ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L23/532 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L23/5226 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/8221 ,  H01L27/0688

Abstract: Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.

公开(公告)号：US11699637B2

公开(公告)日：2023-07-11

申请号：US17547066

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Stephanie A. Bojarski

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

公开(公告)号：US11676966B2

公开(公告)日：2023-06-13

申请号：US16354960

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/17 ,  H01L25/065 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/7851 ,  H01L2224/0401

Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US11664377B2

公开(公告)日：2023-05-30

申请号：US17547147

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Ehren Mannebach ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10

CPC classification number: H01L27/0922 ,  H01L23/5283 ,  H01L29/1033

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US11658221B2

公开(公告)日：2023-05-23

申请号：US17522764

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L21/26513 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US11658072B2

公开(公告)日：2023-05-23

申请号：US17385688

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Sean T. Ma ,  Justin R. Weber ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/683 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/167 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/2252 ,  H01L21/26533 ,  H01L21/6835 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/167 ,  H01L29/401 ,  H01L29/66545 ,  H01L2221/6835

Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

公开(公告)号：US11646352B2

公开(公告)日：2023-05-09

申请号：US16455669

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC: H01L29/417

CPC classification number: H01L29/41741 ,  H01L29/41775

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US11616056B2

公开(公告)日：2023-03-28

申请号：US16649712

申请日：2018-01-18

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/06 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861

Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

公开(公告)号：US11605565B2

公开(公告)日：2023-03-14

申请号：US16236156

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Aaron Lilak ,  Kimin Jun ,  Brennen Mueller ,  Ehren Mannebach ,  Anh Phan ,  Patrick Morrow ,  Hui Jae Yoo ,  Jack T. Kavalieros

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230073078A1

公开(公告)日：2023-03-09

申请号：US17445856

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Sudipto Naskar ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Marko Radosavljevic ,  Nicole K. Thomas ,  Patrick Morrow ,  Urusa Alaan

IPC: H01L27/12

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.