公开(公告)号：US20230005921A1

公开(公告)日：2023-01-05

申请号：US17943038

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: H01L27/108 ,  G11C5/06

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

公开(公告)号：US20240224504A1

公开(公告)日：2024-07-04

申请号：US18089957

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Pushkar RANADE ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H10B12/00

CPC classification number: H01L27/1082 ,  H01L27/10873 ,  H01L29/1608

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222469A1

公开(公告)日：2024-07-04

申请号：US18089966

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66893

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222228A1

公开(公告)日：2024-07-04

申请号：US18089931

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L23/48 ,  H01L21/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/13 ,  H01L25/0657 ,  H01L27/088 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2924/05032 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an SiC layer coupled with devices within a GaN layer proximate to the SiC to convert a high voltage source to the package, e.g. greater than 1 kV, to 1-1.8 V used by components within the package. The devices may be transistors. The voltage conversion will allow increased power to be supplied to the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113025A1

公开(公告)日：2024-04-04

申请号：US17958283

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/5283 ,  H01L29/0673

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.

公开(公告)号：US20240006416A1

公开(公告)日：2024-01-04

申请号：US17855598

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

公开(公告)号：US20240006412A1

公开(公告)日：2024-01-04

申请号：US17855608

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU ,  Cory WEBER ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

公开(公告)号：US20230422485A1

公开(公告)日：2023-12-28

申请号：US17851967

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Cory WEBER ,  Anand S. MURTHY

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/522 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/10841 ,  H01L29/0673 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/78696

Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

公开(公告)号：US20240224508A1

公开(公告)日：2024-07-04

申请号：US18090816

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B12/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B12/36 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78696

Abstract: Structures having bit-cost scaling with relaxed transistor area are described. In an example, an integrated circuit structure includes a plurality of plate lines along a first direction. A transistor is beneath the plurality of plate lines, with a direction of a first source or drain to a gate to a second source or drain of the transistor being a second direction orthogonal to the first direction. A plurality of capacitor structures is over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines. The plurality of capacitor structures has a staggered arrangement from a plan view perspective.

公开(公告)号：US20240224488A1

公开(公告)日：2024-07-04

申请号：US18089865

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H10B10/00 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00

CPC classification number: H10B10/125 ,  H01L23/481 ,  H01L25/0657 ,  H10B12/056

Abstract: Structures having two-level memory are described. In an example, an integrated circuit structure includes an SRAM layer including transistors. A DRAM layer is vertically spaced apart from the transistors of the SRAM layer. A metallization structure is between the transistors of the SRAM layer and the DRAM layer.