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公开(公告)号：US20160163451A1
公开(公告)日：2016-06-09
申请号：US14505474
申请日：2014-10-02
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
CPC classification number: H01F41/042 , H01F27/2804 , H01F27/29
Abstract: In accordance with an embodiment, a circuit element includes a flexible foldable substrate having portions of a first inductor formed on first and second major surfaces of the flexible substrate. In accordance with another embodiment, a first electrically conductive having a first terminal, a second terminal, and a first annular-shaped portion between the first terminal and the second terminal trace is formed on a first portion of the first major surface. A second electrically conductive trace having a first terminal, a second terminal, a first annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace, and a second annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace is formed on the second major surface. The first electrically conductive trace is coupled to the second electrically conductive trace by a thru-via.
Abstract translation: 根据实施例，电路元件包括柔性可折叠基板，其具有形成在柔性基板的第一和第二主表面上的第一电感器的部分。 根据另一个实施例，在第一主表面的第一部分上形成具有第一端子，第二端子和第一端子和第二端子迹线之间的第一环形部分的第一导电体。 第二导电迹线，具有第一端子，第二端子，在第二导电迹线的第一端子和第二端子之间的第一环形部分以及第一端子和第二端子之间的第二环形部分 的第二导电迹线形成在第二主表面上。 第一导电迹线通过通孔耦合到第二导电迹线。
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公开(公告)号：US08890287B2
公开(公告)日：2014-11-18
申请号：US12802012
申请日：2010-05-27
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
IPC: H01L29/92 , H01L21/02 , H01L23/522 , H01L49/02
CPC classification number: H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
Abstract: A high value capacitance per unit area capacitor is fabricated on a substrate 1 by converting a portion of a primary function anti-reflecting conducting layer 36 to a high value dielectric layer 37 by partially oxidizing the conducting layer to form the dielectric layer. The resultant combination is sandwiched between two metal layer electrodes 35 and 55 to complete the capacitor structure.
Abstract translation: 通过将导电层部分氧化形成电介质层，将主功能抗反射导电层36的一部分转换成高价值的电介质层37，在基板1上制造高电容值的单位面积电容器。 所得到的组合夹在两个金属层电极35和55之间以完成电容器结构。
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公开(公告)号：US08879276B2
公开(公告)日：2014-11-04
申请号：US13506110
申请日：2012-03-27
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
CPC classification number: H05K1/189 , H01F2017/006 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/30107 , H05K1/028 , H05K1/165 , H05K1/183 , H05K3/4602 , H05K2201/086 , H05K2201/09063 , H05K2201/09263 , H05K2201/10106 , Y10T29/4902 , Y10T29/49124 , H01L2924/00
Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
Abstract translation: 将嵌入式设备105组装在柔性电路组件30内，使嵌入式设备有意地位于柔性电路组件中心平面115附近，以最小化对嵌入式设备的应力影响。 用于嵌入式装置的开口18在中间层10中放大，以增强柔性电路组件的柔性。
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公开(公告)号：US20140167618A1
公开(公告)日：2014-06-19
申请号：US13694569
申请日：2012-12-13
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
IPC: H05B37/02
CPC classification number: H05B33/0803 , H05B33/0815 , H05B33/0857
Abstract: Intelligent lighting system 100 is configured to operate from an AC source 12. An array of visible light emitting diodes (LEDs) 124 responds to environmental room conditions monitored by a sensor circuit. A microcontroller 146 operates in response to sensor circuit communications to control the state of the visible light array. An internal low noise voltage source VL is derived from the waste heat product from a portion of the LED array. The low noise voltage source is used to power the sensor circuit and the microcontroller.
Abstract translation: 智能照明系统100被配置为从AC源12操作。可见光发射二极管（LED）124的阵列响应于由传感器电路监测的环境房间状态。 微控制器146响应于传感器电路通信而操作以控制可见光阵列的状态。 来自LED阵列的一部分的废热产物导出内部低噪声电压源VL。 低噪声电压源用于为传感器电路和微控制器供电。
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公开(公告)号：US20100301452A1
公开(公告)日：2010-12-02
申请号：US12802012
申请日：2010-05-27
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
CPC classification number: H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
Abstract: A high value capacitance per unit area capacitor is fabricated on a substrate 1 by converting a portion of a primary function anti-reflecting conducting layer 36 to a high value dielectric layer 37 by partially oxidizing the conducting layer to form the dielectric layer. The resultant combination is sandwiched between two metal layer electrodes 35 and 55 to complete the capacitor structure.
Abstract translation: 通过将导电层部分氧化形成电介质层，将主功能抗反射导电层36的一部分转换成高价值的电介质层37，在基板1上制造高电容值的单位面积电容器。 所得到的组合夹在两个金属层电极35和55之间以完成电容器结构。
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Patent Agency Ranking
公开(公告)号：US07208841B2
公开(公告)日：2007-04-24
申请号：US10909124
申请日：2004-07-30
Applicant: James Jen-Ho Wang , Jin-Wook Jang , Alfredo Mendoza , Rajashi Runton , Russell Shumway
Inventor： James Jen-Ho Wang , Jin-Wook Jang , Alfredo Mendoza , Rajashi Runton , Russell Shumway
CPC classification number: H01L24/16 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02335 , H01L2224/0401 , H01L2224/081 , H01L2224/1147 , H01L2224/13027 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/00012
Abstract: A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation layer (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.
Abstract translation: 提供半导体器件（51）。 所述装置（51）包括其上具有接触垫（61）的模具（53），具有与所述接触垫（61）电连通的基部（64）的再分配导体（59）和横向延伸部分 （63），与再分布导体（59）电连通的凸起触头（65）和设置在再分布导体（59）的横向延伸部分（63）和模具（...）之间的钝化层（57） 53）。 优选地，再分配导体（59）被卷积并且适于在足够的应力下从钝化层（57）剥离或分层，使得其可以相对于钝化层（57）和基部（64）移动以减轻机械应力 在基板（69）和模具（53）之间。 容纳小CTE失配应变而不会发生故障的凸起和卷绕再分配导体（59）允许DCA倒装芯片可靠，无需底部填充或额外的组装过程。
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公开(公告)号：US10685944B2
公开(公告)日：2020-06-16
申请号：US15790057
申请日：2017-10-23
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
IPC: H01L25/16 , G01K7/01 , H01L23/46 , H01L23/32 , H01L25/00 , G01K7/22 , H01L23/13 , H01L23/00 , H01L23/14
Abstract: In accordance with an embodiment, sensor structure has a first, second, and third laminated structures. The second laminated structure is positioned between the first laminated structure and the third laminated structure. The first laminated structure includes a first portion of a first sensing element and the third laminated structure includes a second portion of the first sensing element. The second laminated structure includes spacer elements that can be used to adjust the sensitivity of the sensor structure.
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公开(公告)号：US20160126010A1
公开(公告)日：2016-05-05
申请号：US14531079
申请日：2014-11-03
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
CPC classification number: H01F41/0206 , H01F17/0013 , H01F41/046 , H01F2017/006 , H01F2017/0066 , H05B33/0803 , H05B33/0821 , H05B33/0845 , H05K1/0209 , H05K1/021 , H05K1/0271 , H05K1/028 , H05K1/0283 , H05K1/165 , H05K1/183 , H05K1/189 , H05K3/0005 , H05K3/0035 , H05K3/0061 , H05K3/0097 , H05K3/281 , H05K3/427 , H05K3/4697 , H05K2201/056 , H05K2201/086 , H05K2201/0919 , H05K2201/09672 , H05K2201/09709 , H05K2201/09845 , H05K2203/0126 , H05K2203/0384 , H05K2203/0571 , H05K2203/063 , H05K2203/1545
Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
Abstract translation: 将嵌入式设备105组装在柔性电路组件30内，使嵌入式设备有意地位于柔性电路组件中心平面115附近，以最小化对嵌入式设备的应力影响。 用于嵌入式装置的开口18在中间层10中放大，以增强柔性电路组件的柔性。
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公开(公告)号：US20120320532A1
公开(公告)日：2012-12-20
申请号：US13506110
申请日：2012-03-27
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
CPC classification number: H05K1/189 , H01F2017/006 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/30107 , H05K1/028 , H05K1/165 , H05K1/183 , H05K3/4602 , H05K2201/086 , H05K2201/09063 , H05K2201/09263 , H05K2201/10106 , Y10T29/4902 , Y10T29/49124 , H01L2924/00
Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
Abstract translation: 将嵌入式设备105组装在柔性电路组件30内，使嵌入式设备有意地位于柔性电路组件中心平面115附近，以最小化对嵌入式设备的应力影响。 用于嵌入式装置的开口18在中间层10中放大，以增强柔性电路组件的柔性。
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公开(公告)号：US07705440B2
公开(公告)日：2010-04-27
申请号：US11851857
申请日：2007-09-07
Applicant: James Jen-Ho Wang
Inventor： James Jen-Ho Wang
CPC classification number: H01L25/50 , H01L21/76898 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2225/06513 , H01L2225/06541 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/00
Abstract: An annular trench region is formed at a semiconductor substrate of an electronic device that defines a conductive plug of the through-wafer via, wherein the conductive plug includes an undisturbed portion of the semiconductor substrate.
Abstract translation: 环形沟槽区形成在限定贯通晶片通孔的导电插塞的电子器件的半导体衬底上，其中导电插塞包括半导体衬底的未受干扰的部分。
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