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公开(公告)号：US09692435B2
公开(公告)日：2017-06-27
申请号：US15130636
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/1023 , H03M1/0607 , H03M1/68
Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.
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公开(公告)号：US10291246B2
公开(公告)日：2019-05-14
申请号：US15633157
申请日：2017-06-26
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.
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公开(公告)号：US10158368B2
公开(公告)日：2018-12-18
申请号：US15997336
申请日：2018-06-04
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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公开(公告)号：US20180287624A1
公开(公告)日：2018-10-04
申请号：US15997336
申请日：2018-06-04
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/0624 , H03M1/66
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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Patent Agency Ranking
15.发明授权公开(公告)号：US09762256B2
公开(公告)日：2017-09-12
申请号：US15130617
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
CPC classification number: H03M1/066 , H03M1/1038 , H03M1/66
Abstract: Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).
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16.发明申请公开(公告)号：US20180226980A1
公开(公告)日：2018-08-09
申请号：US15949395
申请日：2018-04-10
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
CPC classification number: H03M1/066 , H03M1/1038 , H03M1/66
Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.
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公开(公告)号：US09991899B2
公开(公告)日：2018-06-05
申请号：US15790343
申请日：2017-10-23
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/0624 , H03M1/66
Abstract: Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.
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公开(公告)号：US09800254B2
公开(公告)日：2017-10-24
申请号：US15130602
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/0624 , H03M1/66
Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with partial constant switching. A digital-to-analog converter (DAC) comprising a plurality of conversion elements may be configured to apply constant switching in only some of the conversion elements. Only conversion elements applying constant switching may incorporate circuitry for providing such the constant switching. Alternatively, each conversion element may incorporate constant switching circuitry and functionality, and the constant switching may then be turned on or off for each conversion element adaptively, such as based on input conditions.
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公开(公告)号：US20160308547A1
公开(公告)日：2016-10-20
申请号：US15130636
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/1023 , H03M1/0607 , H03M1/68
Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.
Abstract translation: 为具有数字偏移量的数模转换器（DAC）提供了系统和方法。 数字偏移可以应用于数模转换器（DAC）的输入端，然后通过DAC将数模转换应用于具有数字偏移量的输入。 数字偏移被设置为考虑与DAC的输入相关的一个或多个条件，其中一个或多个条件影响DAC中的多个转换元件中的一个或多个的开关特性，并且其中每个转换元件处理特定 位到DAC的输入。 数字偏移可以被动态地和自适应地确定，例如基于与输入有关的输入和/或条件。 或者，数字偏移可以是预定的和固定的。 一个或多个调整可以选择性地应用于特定输入条件的数字偏移。
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