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公开(公告)号：US09331725B2
公开(公告)日：2016-05-03
申请号：US14589801
申请日：2015-01-05
Applicant: Maxlinear, Inc.
CPC classification number: H04B1/0475 , H03F1/02 , H03F1/3241 , H03F1/3247 , H03F3/195 , H03F3/213 , H03F3/24 , H03F2200/451 , H03F2201/3215 , H03G3/3042 , H04B2001/0425 , H04B2001/045
Abstract: Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, generating a conditioned waveform by adding the error signal to the original waveform, and amplifying the conditioned waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain. The error signal may be filtered utilizing a distortion shaping filter.
Abstract translation: 用于波峰因数降低的方法和系统可以包括产生原始波形，通过减小原始波形的波峰因数产生失真信号，通过从失真信号中减去原始波形产生误差信号，通过将 误差信号到原始波形，并放大调节波形。 可以基于光谱掩模要求来减小原始波形的波峰因数。 原始波形的波峰因数可以使用限幅器来减小。 功率放大器可以包括可编程增益放大器（PGA）。 可以基于PGA模型和/或预失真模型来生成失真信号。 来自PA的输出的信号可以被反馈到PGA模型。 PGA模型可以动态配置。 在模拟域和/或数字域中，原始波形的波峰因数可能会降低。 可以使用失真整形滤波器对误差信号进行滤波。
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公开(公告)号：US20220166323A1
公开(公告)日：2022-05-26
申请号：US17403765
申请日：2021-08-16
Applicant: MAXLINEAR, INC.
Inventor： Curtis Ling , Shantha Murthy Prem Swaroop , Vinit Jayaraj
Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.
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公开(公告)号：US10291246B2
公开(公告)日：2019-05-14
申请号：US15633157
申请日：2017-06-26
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.
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公开(公告)号：US10158368B2
公开(公告)日：2018-12-18
申请号：US15997336
申请日：2018-06-04
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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公开(公告)号：US20180287624A1
公开(公告)日：2018-10-04
申请号：US15997336
申请日：2018-06-04
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/0624 , H03M1/66
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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Patent Agency Ranking
公开(公告)号：US20170310347A1
公开(公告)日：2017-10-26
申请号：US15646773
申请日：2017-07-11
Applicant: Maxlinear, Inc.
CPC classification number: H04B1/0475 , H03F1/02 , H03F1/3241 , H03F1/3247 , H03F3/195 , H03F3/213 , H03F3/24 , H03F2200/451 , H03F2201/3215 , H03G3/3042 , H04B2001/0425 , H04B2001/045
Abstract: Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, and generating a conditioned waveform by adding the error signal to the original waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain.
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17.发明授权公开(公告)号：US09762256B2
公开(公告)日：2017-09-12
申请号：US15130617
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
CPC classification number: H03M1/066 , H03M1/1038 , H03M1/66
Abstract: Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).
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公开(公告)号：US12027981B2
公开(公告)日：2024-07-02
申请号：US17403765
申请日：2021-08-16
Applicant: MAXLINEAR, INC.
Inventor： Curtis Ling , Shantha Murthy Prem Swaroop , Vinit Jayaraj
CPC classification number: H02M3/1584 , H02M3/156 , H02M3/1586 , H03M1/143
Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.
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公开(公告)号：US11095223B2
公开(公告)日：2021-08-17
申请号：US16665563
申请日：2019-10-28
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Shantha Murthy Prem Swaroop , Vinit Jayaraj
Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.
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公开(公告)号：US20190115929A1
公开(公告)日：2019-04-18
申请号：US16217348
申请日：2018-12-12
Applicant: Maxlinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
IPC: H03M1/06
CPC classification number: H03M1/0624 , H03M1/66
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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