公开(公告)号：US12230560B2

公开(公告)日：2025-02-18

申请号：US17546191

申请日：2021-12-09

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065

Abstract: A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.

公开(公告)号：US11908759B2

公开(公告)日：2024-02-20

申请号：US17190584

申请日：2021-03-03

Applicant: MediaTek Inc.

Inventor： Nan-Cheng Chen ,  Che-Ya Chou ,  Hsing-Chih Liu ,  Che-Hung Kuo

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/04 ,  H01L23/14 ,  H01L25/18

CPC classification number: H01L23/31 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/157 ,  H01L2924/15311 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

公开(公告)号：US11887976B2

公开(公告)日：2024-01-30

申请号：US17494851

申请日：2021-10-06

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Yi-Jyun Lee

IPC: H01L23/498 ,  H01L27/01 ,  H01L25/065 ,  H01L23/58 ,  H01L49/02

CPC classification number: H01L27/01 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/585 ,  H01L28/40 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06572

Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

公开(公告)号：US20210351124A1

公开(公告)日：2021-11-11

申请号：US17179357

申请日：2021-02-18

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu

IPC: H01L23/522 ,  H01L23/31

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

公开(公告)号：US10199318B2

公开(公告)日：2019-02-05

申请号：US15481500

申请日：2017-04-07

Applicant: MEDIATEK INC.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Che-Hung Kuo ,  Che-Ya Chou ,  Wei-Che Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.

公开(公告)号：US09818727B2

公开(公告)日：2017-11-14

申请号：US15012018

申请日：2016-02-01

Applicant: MediaTek Inc.

Inventor： Che-Hung Kuo ,  Ying-Chih Chen ,  Che-Ya Chou

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48265 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

公开(公告)号：US12165961B2

公开(公告)日：2024-12-10

申请号：US18329721

申请日：2023-06-06

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

公开(公告)号：US20230422525A1

公开(公告)日：2023-12-28

申请号：US18203666

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H10B12/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H10B12/00 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

公开(公告)号：US11776899B2

公开(公告)日：2023-10-03

申请号：US17179357

申请日：2021-02-18

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu

IPC: H01L23/522 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L23/3114 ,  H01L23/3128

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

公开(公告)号：US11721882B2

公开(公告)日：2023-08-08

申请号：US17075561

申请日：2020-10-20

Applicant: MediaTek Inc.

Inventor： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01Q1/2283 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16141 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19042 ,  H01L2924/19106

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.