公开(公告)号：US11960735B2

公开(公告)日：2024-04-16

申请号：US17464576

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： David G. Springberg

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.

公开(公告)号：US11854637B2

公开(公告)日：2023-12-26

申请号：US18103603

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Michael R. Spica ,  David G. Springberg

IPC: G11C29/00 ,  G11C29/10 ,  G06F9/30 ,  G06F11/22 ,  G11C29/14

CPC classification number: G11C29/10 ,  G06F9/30101 ,  G06F11/221 ,  G11C29/14

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.

公开(公告)号：US20220083265A1

公开(公告)日：2022-03-17

申请号：US17537446

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： David G. Springberg ,  David Sluiter

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F12/02

Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold. The processing device further writes the second write data from the internal SRAM device as a second programming unit to the one or more NVM devices.