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    Electronic device comprising conductive material and ferroelectric material
    11.
    发明授权
    Electronic device comprising conductive material and ferroelectric material 有权

    公开(公告)号：US11469043B2

    公开(公告)日：2022-10-11

    申请号：US17183285

    申请日：2021-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Ashonita A. Chavan

    IPC: H01L21/02 ,  H01G4/10 ,  H01G4/30 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/11507 ,  H01G4/33 ,  H01L29/78 ,  H01L49/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/40

    Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

    Method used in forming an electronic device comprising conductive material and ferroelectric material
    12.
    发明授权
    Method used in forming an electronic device comprising conductive material and ferroelectric material 有权

    公开(公告)号：US10950384B2

    公开(公告)日：2021-03-16

    申请号：US15691541

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Ashonita A. Chavan

    IPC: H01F7/06 ,  H01G4/10 ,  H01G4/30 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/11507 ,  H01G4/33 ,  H01L29/78 ,  H01L49/02 ,  H01L21/28 ,  H01L29/51

    Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

    Transistor And Methods Of Forming Transistors
    13.
    发明申请
    Transistor And Methods Of Forming Transistors 有权

    公开(公告)号：US20210043768A1

    公开(公告)日：2021-02-11

    申请号：US16536479

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Darwin Franseda Fan ,  Ali Moballegh

    IPC: H01L29/78 ,  H01L27/108 ,  H01L29/04 ,  H01L21/02 ,  H01L29/66

    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.

    Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb
    14.
    发明申请
    Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb 审中-公开

    公开(公告)号：US20190189357A1

    公开(公告)日：2019-06-20

    申请号：US15843278

    申请日：2017-12-15

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Beth R. Cook ,  Manuj Nahar ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01G4/38 ,  G11C11/22 ,  H01L27/11507

    CPC classification number: H01G4/385 ,  G11C11/221 ,  H01L27/11507

    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

    SINGLE-CRYSTAL TRANSISTORS FOR MEMORY DEVICES
    15.
    发明公开
    SINGLE-CRYSTAL TRANSISTORS FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240105766A1

    公开(公告)日：2024-03-28

    申请号：US18531525

    申请日：2023-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

    IPC: H01L29/04 ,  H01L29/10

    CPC classification number: H01L29/04 ,  H01L29/1033 ,  H10B12/00

    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

    SEMICONDUCTOR DEVICES COMPRISING CONTINUOUS CRYSTALLINE STRUCTURES, AND RELATED MEMORY DEVICES AND SYSTEMS
    20.
    发明申请
    SEMICONDUCTOR DEVICES COMPRISING CONTINUOUS CRYSTALLINE STRUCTURES, AND RELATED MEMORY DEVICES AND SYSTEMS 有权

    公开(公告)号：US20210265466A1

    公开(公告)日：2021-08-26

    申请号：US17319563

    申请日：2021-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Michael Mutch ,  Manuj Nahar

    IPC: H01L29/161 ,  H01L29/04 ,  H01L29/786 ,  H01L21/02 ,  C30B25/18

    Abstract: A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.

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