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公开(公告)号:US20190221258A1
公开(公告)日:2019-07-18
申请号:US16361313
申请日:2019-03-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Preston A. Thomson , Peiling Zhang , Junchao Chen
CPC classification number: G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
Abstract: Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell.
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公开(公告)号:US20180019014A1
公开(公告)日:2018-01-18
申请号:US15490316
申请日:2017-04-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Preston A. Thomson , Peiling Zhang , Junchao Chen
CPC classification number: G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
Abstract: Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different than the first operating mode.
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公开(公告)号:US11721404B2
公开(公告)日:2023-08-08
申请号:US17484777
申请日:2021-09-24
Applicant: Micron Technology, Inc.
Inventor: Kishore K. Muchherla , Ashutosh Malshe , Preston A. Thomson , Michael G. Miller , Gary F. Besinga , Scott A. Stoller , Sampath K. Ratnam , Renato C. Padilla , Peter Feeley
CPC classification number: G11C16/349 , G11C16/12 , G11C2211/5641
Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
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公开(公告)号:US11443811B2
公开(公告)日:2022-09-13
申请号:US17074758
申请日:2020-10-20
Applicant: Micron Technology, Inc.
Inventor: Kevin R. Brandt , Adam J. Hieb , Jonathan Tanguy , Preston A. Thomson
Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.
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公开(公告)号:US11200925B2
公开(公告)日:2021-12-14
申请号:US16946305
申请日:2020-06-16
Applicant: Micron Technology, Inc.
Inventor: Jonathan Wen Jian Oh , Aaron James Olson , Fulvio Rori , Qisong Lin , Preston A. Thomson
IPC: G11C7/10 , G06F12/0882 , G06F9/30 , G06F11/27
Abstract: A programmable memory device includes a read only memory (ROM) block to store instructions associated with functionality of the programmable memory device. The device includes a memory array having a set of reserved pages to store updates to be performed on the ROM block. The device includes a controller coupled to the ROM block and the memory array. The controller is to execute the instructions to: execute a set features command; program, in execution of the set features command, a set of sub-feature parameters to a specified feature address of the set of reserved pages, wherein the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and program a REM-profiled page of the set of reserved pages with REM data received from a host system.
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公开(公告)号:US11042306B2
公开(公告)日:2021-06-22
申请号:US16420505
申请日:2019-05-23
Applicant: Micron Technology, Inc.
Inventor: Kishore K. Muchherla , Ashutosh Malshe , Preston A. Thomson , Michael G. Miller , Sampath K. Ratnam , Renato C. Padilla , Peter Feeley
Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
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公开(公告)号:US20180341605A1
公开(公告)日:2018-11-29
申请号:US16054189
申请日:2018-08-03
Applicant: Micron Technology, Inc.
Inventor: Preston A. Thomson , Kishore K. Muchherla , Sampath K. Ratnam
CPC classification number: G06F13/24 , G06F11/1405 , G11C16/0483 , G11C16/102
Abstract: The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.
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公开(公告)号:US10042789B2
公开(公告)日:2018-08-07
申请号:US14662280
申请日:2015-03-19
Applicant: Micron Technology, Inc.
Inventor: Preston A. Thomson , Kishore K. Muchherla , Sampath K. Ratnam
Abstract: The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.
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公开(公告)号:US20230005548A1
公开(公告)日:2023-01-05
申请号:US17943139
申请日:2022-09-12
Applicant: Micron Technology, Inc.
Inventor: Kevin R. Brandt , Adam J. Hieb , Jonathan Tanguy , Preston A. Thomson
Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.
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公开(公告)号:US20220013182A1
公开(公告)日:2022-01-13
申请号:US17484777
申请日:2021-09-24
Applicant: Micron Technology, Inc.
Inventor: Kishore K. Muchherla , Ashutosh Malshe , Preston A. Thomson , Michael G. Miller , Gary F. Besinga , Scott A. Stoller , Sampath K. Ratnam , Renato C. Padilla , Peter Feeley
IPC: G11C16/34
Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
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