公开(公告)号：US20250028660A1

公开(公告)日：2025-01-23

申请号：US18452554

申请日：2023-08-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/02 ,  G11C29/04

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to adjust the timing of at least one of the respective set of data signals by an amount based on at least one module control signal in a previous operation.

公开(公告)号：US11994982B2

公开(公告)日：2024-05-28

申请号：US17202021

申请日：2021-03-15

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G11C8/12 ,  G06F12/00 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n

公开(公告)号：US11862267B2

公开(公告)日：2024-01-02

申请号：US16286246

申请日：2019-02-26

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/10 ,  G11C29/12 ,  G11C5/04

CPC classification number: G11C29/10 ,  G11C29/12 ,  G11C5/04

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.

公开(公告)号：US11762788B2

公开(公告)日：2023-09-19

申请号：US17114478

申请日：2020-12-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C8/18 ,  G11C16/00 ,  G11C29/02 ,  G11C7/20 ,  G11C8/12 ,  G11C29/04

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  H05K999/99 ,  G11C7/109 ,  G11C7/20 ,  G11C8/12 ,  G11C2029/0407

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

公开(公告)号：US20220253380A1

公开(公告)日：2022-08-11

申请号：US17531743

申请日：2021-11-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06

Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

公开(公告)号：US20210382834A1

公开(公告)日：2021-12-09

申请号：US17403832

申请日：2021-08-16

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G11C5/04 ,  G06F13/00 ,  G06F12/00 ,  G06F13/42 ,  G11C7/10 ,  G11C15/00

Abstract: A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

公开(公告)号：US10949339B2

公开(公告)日：2021-03-16

申请号：US15470856

申请日：2017-03-27

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

Abstract: A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.

公开(公告)号：US10884923B2

公开(公告)日：2021-01-05

申请号：US16432700

申请日：2019-06-05

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

Abstract: A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.

公开(公告)号：US10217523B1

公开(公告)日：2019-02-26

申请号：US14229844

申请日：2014-03-29

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/00 ,  G11C29/10

Abstract: A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board; and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes including a normal mode and a test mode. During the normal mode, the control module provides the address and control signals based on address and control signals from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.

公开(公告)号：US20170147514A1

公开(公告)日：2017-05-25

申请号：US15426064

申请日：2017-02-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G11C8/18 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.