公开(公告)号：US10979176B1

公开(公告)日：2021-04-13

申请号：US16792154

申请日：2020-02-14

Applicant: NVIDIA Corp.

Inventor： Sunil Sudhakaran ,  Rohit Rathi

IPC: H04L1/00 ,  H04L1/08 ,  H04L25/03

Abstract: Techniques for limiting the growth of errors in decoded data words that arise from bit errors incurred during transmission. The growth of 3+ bit errors in the decoded data word is limited at the expense of a higher number of two bit errors, which are correctable using practical error correcting codes.

公开(公告)号：US10594337B2

公开(公告)日：2020-03-17

申请号：US16557637

申请日：2019-08-30

Applicant: NVIDIA Corp.

Inventor： Sunil Sudhakaran ,  Russ Newcomb ,  Rohit Rathi

IPC: H04L27/00 ,  H04L27/06 ,  H03M5/14 ,  H03M5/08 ,  H03M7/46

Abstract: A circuit includes a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus, a decoder to generate output data comprising N-L bits of each N-bit transmission, and a delay circuit to apply the L bits for a previous transmission to control the inversion of a current transmission at the decoder.