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公开(公告)号：US20220262447A1
公开(公告)日：2022-08-18
申请号：US17670226
申请日：2022-02-11
Applicant: NVIDIA Corp.
Inventor： Sunil Sudhakaran , Gautam Bhatia , Robert Bloemer
Abstract: First symbols are generated on a plurality of data channels by applying PAM-N encoding on a first subset of bits of a data burst, the first symbols generated without maximum transitions; second symbols are generated on at least one optionally-activated additional data channel, the second symbols generated by applying the PAM-N encoding on a second subset of bits of the data burst, the second symbols generated without maximum transitions; and third symbols are generated on a channel for communicating error correction bits for the first bits and second bits, the third symbols generated by applying hybrid PAM-N encoding on the error correction bits and a third subset of bits of the data burst, the hybrid PAM-N encoding comprising an interleaving of symbols with N voltage levels and symbols with less than N voltage levels.
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公开(公告)号：US20190386677A1
公开(公告)日：2019-12-19
申请号：US16557637
申请日：2019-08-30
Applicant: NVIDIA Corp.
Inventor： Sunil Sudhakaran , Russ Newcomb , Rohit Rathi
Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.
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公开(公告)号：US12135607B2
公开(公告)日：2024-11-05
申请号：US18186464
申请日：2023-03-20
Applicant: NVIDIA Corp.
Inventor： Gautam Bhatia , Sunil Sudhakaran , Kyutaeg Oh
Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.
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公开(公告)号：US20200028708A1
公开(公告)日：2020-01-23
申请号：US16190467
申请日：2018-11-14
Applicant: NVIDIA Corp.
Inventor： John Wilson , Sunil Sudhakaran
Abstract: An encoding process for bus data utilizes data from multiple data line groups on a multi-byte wide bus where each group has an associated DBI line. The process leverages the expanded encoding space for the multiple groups and associated multiple DBI bits. This process may be expanded to four bytes, eight bytes, etc.
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公开(公告)号：US20190229749A1
公开(公告)日：2019-07-25
申请号：US16124085
申请日：2018-09-06
Applicant: NVIDIA Corp.
Inventor： Sunil Sudhakaran , Russ Newcomb , Rohit Rathi
Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.
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Patent Agency Ranking
公开(公告)号：US12197281B2
公开(公告)日：2025-01-14
申请号：US18459215
申请日：2023-08-31
Applicant: NVIDIA Corp.
Inventor： Gautam Bhatia , Sunil Sudhakaran , Kyutaeg Oh
Abstract: A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.
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公开(公告)号：US12132590B2
公开(公告)日：2024-10-29
申请号：US17931062
申请日：2022-09-09
Applicant: NVIDIA Corp.
Inventor： Sunil Sudhakaran
CPC classification number: H04L25/4917 , H03M13/1111 , H03M13/611 , H04L1/0061
Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels, one or more auxiliary data channels, and an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on an error correction channel.
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公开(公告)号：US20230327924A1
公开(公告)日：2023-10-12
申请号：US17931062
申请日：2022-09-09
Applicant: NVIDIA Corp.
Inventor： Sunil Sudhakaran
CPC classification number: H04L25/4917 , H04L1/0061 , H03M13/1111 , H03M13/611
Abstract: Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
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公开(公告)号：US20230297466A1
公开(公告)日：2023-09-21
申请号：US18186464
申请日：2023-03-20
Applicant: NVIDIA Corp.
Inventor： Gautam Bhatia , Sunil Sudhakaran , Kyutaeg Oh
CPC classification number: G06F11/1004 , G06F11/1068 , G06F11/0787
Abstract: Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
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公开(公告)号：US20230418705A1
公开(公告)日：2023-12-28
申请号：US18459215
申请日：2023-08-31
Applicant: NVIDIA Corp.
Inventor： Gautam Bhatia , Sunil Sudhakaran , Kyutaeg Oh
CPC classification number: G06F11/1004 , G06F11/0787 , G06F11/1068
Abstract: A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.
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