公开(公告)号：US20160320973A1

公开(公告)日：2016-11-03

申请号：US14751147

申请日：2015-06-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/349 ,  G11C2211/5641

Abstract: A data writing method for a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same are provided. The method includes grouping physical erasing units of the rewritable non-volatile memory module into a temporary area and a storage area. The method also includes selecting a first physical erasing unit from the temporary area, copying a plurality of valid data of the first physical erasing unit to a second physical erasing unit of the temporary area, and performing an erasing operation on the first physical erasing unit. The method further includes selecting a third physical erasing unit from the temporary area, copying a plurality of valid data of the third physical erasing unit to a forth physical erasing unit of the storage area, and performing the erasing operation on the third physical erasing unit.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法，以及存储器控制电路单元和使用其的存储器存储装置。 该方法包括将可重写非易失性存储器模块的物理擦除单元分组成临时区域和存储区域。 该方法还包括从临时区域选择第一物理擦除单元，将第一物理擦除单元的多个有效数据复制到临时区域的第二物理擦除单元，并对第一物理擦除单元进行擦除操作。 该方法还包括从临时区域选择第三物理擦除单元，将第三物理擦除单元的多个有效数据复制到存储区域的第四物理擦除单元，以及对第三物理擦除单元进行擦除操作。

公开(公告)号：US09304907B2

公开(公告)日：2016-04-05

申请号：US14510130

申请日：2014-10-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: A data management method is provided, and the method includes: receiving first data and identifying a first address. The method also includes: determining whether the first data is incompressible; and, if the first data is incompressible, determining whether the first address is meeting a requirement of start address. The method further includes: if the first address is not meeting the requirement of start address, storing the padding data starting from the first address, and storing the first data starting from a following address, wherein the following address is meeting the requirement of start address.

Abstract translation: 提供了数据管理方法，该方法包括：接收第一数据并识别第一地址。 该方法还包括：确定第一数据是否不可压缩; 并且如果第一数据不可压缩，则确定第一地址是否满足起始地址的要求。 该方法还包括：如果第一地址不满足开始地址的要求，则从第一地址开始存储填补数据，并从下一个地址开始存储第一个数据，其中以下地址满足起始地址的要求 。

公开(公告)号：US20160034388A1

公开(公告)日：2016-02-04

申请号：US14510130

申请日：2014-10-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: A data management method is provided, and the method includes: receiving first data and identifying a first address. The method also includes: determining whether the first data is incompressible; and, if the first data is incompressible, determining whether the first address is meeting a requirement of start address. The method further includes: if the first address is not meeting the requirement of start address, storing the padding data starting from the first address, and storing the first data starting from a following address, wherein the following address is meeting the requirement of start address.

Abstract translation: 提供了数据管理方法，该方法包括：接收第一数据并识别第一地址。 该方法还包括：确定第一数据是否不可压缩; 并且如果第一数据不可压缩，则确定第一地址是否满足起始地址的要求。 该方法还包括：如果第一地址不满足开始地址的要求，则从第一地址开始存储填补数据，并从下一个地址开始存储第一个数据，其中以下地址满足起始地址的要求 。

公开(公告)号：US09146805B2

公开(公告)日：2015-09-29

申请号：US14038778

申请日：2013-09-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1044

Abstract: A data protecting method, a memory storage device, and a memory controller are provided for a rewritable non-volatile memory module. The data protecting method includes: generating a first error correcting code by using data stored in first memory cells of a plurality of memory cells. The first memory cells are located on first word lines and first bit lines. Among the memory cells located on each of the first bit lines, only one of the memory cells stores the data used to generate the first error correcting code. Accordingly, the data in the memory cells is efficiently protected.

Abstract translation: 为可重写非易失性存储器模块提供数据保护方法，存储器存储设备和存储器控制器。 数据保护方法包括：通过使用存储在多个存储单元的第一存储单元中的数据来产生第一纠错码。 第一存储单元位于第一字线和第一位线上。 在位于每个第一位线上的存储器单元之中，只有一个存储器单元存储用于生成第一纠错码的数据。 因此，有效地保护了存储单元中的数据。

公开(公告)号：US09086954B2

公开(公告)日：2015-07-21

申请号：US13717723

申请日：2012-12-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G06F11/10

CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7211

Abstract: A data storing method for a memory storage apparatus having a flash memory module is provided. The method includes detecting the operating temperature of the memory storage device through a thermal sensor and determining whether the operating temperature of the memory storage device is larger than a predetermined temperature. The methods further includes using a first data storing mode to access the flash memory module if the operating temperature of the memory storage device is not larger than the predetermined temperature; and using a second data storing mode to access the flash memory module if the operating temperature of the memory storage apparatus is larger than the predetermined temperature, wherein the first data storing mode is different from the second data storing mode. Accordingly, the method can effectively ensure the accuracy of the data stored into the flash memory module.

Abstract translation: 提供一种具有闪速存储器模块的存储器存储装置的数据存储方法。 该方法包括通过热传感器检测存储器存储装置的工作温度，并确定存储器存储装置的工作温度是否大于预定温度。 所述方法还包括如果所述存储器存储设备的工作温度不大于所述预定温度，则使用第一数据存储模式来访问所述闪存模块; 以及如果所述存储器存储装置的工作温度大于所述预定温度，则使用第二数据存储模式访问所述闪存模块，其中所述第一数据存储模式与所述第二数据存储模式不同。 因此，该方法可以有效地确保存储到闪存模块中的数据的准确性。

公开(公告)号：US20150161039A1

公开(公告)日：2015-06-11

申请号：US14166815

申请日：2014-01-28

Applicant: Phison Electronics Corp.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F21/79 ,  G06F2003/0697 ,  G06F2212/1052 ,  G06F2212/7205 ,  G06F2221/2143

Abstract: A data erasing method for a rewritable non-volatile memory module is provided. The method includes receiving a predetermined command for performing on a first logical sub-unit from a host system; marking a first physical programming unit mapped to the first logical sub-unit as being in an invalid data status and recording a mark for a first physical erasing unit that the first physical programming unit belongs to, in response to the predetermined command. The method further includes selecting the first physical erasing unit according to the mark, copying valid data in the first physical erasing unit to a second physical erasing unit gotten from a spare area of the rewritable non-volatile memory module and erasing data stored in the first physical erasing unit.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据擦除方法。 该方法包括从主机系统接收用于在第一逻辑子单元上执行的预定命令; 将第一物理编程单元映射到处于无效数据状态的第一逻辑子单元，并响应于预定命令，记录第一物理编程单元所属的第一物理擦除单元的标记。 该方法还包括根据该标记选择第一物理擦除单元，将第一物理擦除单元中的有效数据复制到从可重写非易失性存储器模块的备用区获得的第二物理擦除单元，并擦除存储在第一物理擦除单元 物理擦除单元。

公开(公告)号：US09037813B2

公开(公告)日：2015-05-19

申请号：US14072517

申请日：2013-11-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Hua Chu ,  Chih-Kang Yeh

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/79

CPC classification number: G06F12/0246 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/1408 ,  G06F21/79 ,  G06F2212/7201

Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

Abstract translation: 提供数据访问方法，以及存储系统和使用该方法的控制器。 数据访问方法适用于具有数据扰动模块的闪存存储系统。 数据访问方法包括从主机接收读取命令并从读取命令获得要读取的逻辑块和要读取的页面。 数据存取方法还包括确定与要读取的逻辑块相对应的数据区中的物理块是否为新块，并且当与待读取的逻辑块相对应的物理块为新时，将该预定数据发送给主机 块。 由此，防止主机从具有数据扰动模块的闪速存储器存储系统读取乱码。

公开(公告)号：US20240192868A1

公开(公告)日：2024-06-13

申请号：US18162724

申请日：2023-02-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: in a first operation mode, setting a physical management unit to cross N physical regions in a rewritable non-volatile memory module; in a second operation mode, setting the physical management unit to cross M physical regions in the rewritable non-volatile memory module, wherein N is greater than M; and accessing the rewritable non-volatile memory module based on the physical management unit.

公开(公告)号：US11687444B2

公开(公告)日：2023-06-27

申请号：US16600568

申请日：2019-10-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0882

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0882 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A data managing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: receiving a write command for writing a plurality of first data into a rewritable non-volatile memory module; when the plurality of first data are continuous data, writing the plurality of first data respectively into a plurality of first physical erasing units by using a single-page programming mode, and recording first management information corresponding to the plurality of first physical erasing units; and when the plurality of first data are not the continuous data, writing the plurality of first data respectively into a plurality of second physical erasing units by using the single-page programming mode.

公开(公告)号：US20220245024A1

公开(公告)日：2022-08-04

申请号：US17184611

申请日：2021-02-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.