公开(公告)号：US11004498B2

公开(公告)日：2021-05-11

申请号：US16568193

申请日：2019-09-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C11/4063 ,  G11C7/10 ,  G11C29/44 ,  G11C5/06

Abstract: A memory interface circuit, a memory storage device and a configuration status checking method are provided. The memory interface circuit is configured to connect a plurality of volatile memory modules and a memory controller. The volatile memory modules include a first volatile memory module and a second volatile memory module. The memory interface circuit includes a first interface circuit and a second interface circuit. The first interface circuit is configured to receive a first signal from the first volatile memory module and transmit a second signal to the second interface circuit through an internal path of the memory interface circuit. The second interface circuit is configured to transmit a third signal to the second volatile memory module according to the second signal to evaluate a configuration status of the memory interface circuit by the third signal.

公开(公告)号：US10978120B2

公开(公告)日：2021-04-13

申请号：US16565407

申请日：2019-09-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C7/22 ,  G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4076

Abstract: A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.

公开(公告)号：US10942541B1

公开(公告)日：2021-03-09

申请号：US16656524

申请日：2019-10-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G06F1/06 ,  H04L7/033 ,  G11C8/18 ,  G11C11/4076 ,  G06F1/08 ,  H03K5/135 ,  H03L7/085 ,  G11C29/02 ,  G11C7/22 ,  H03L7/00 ,  G06F13/16

Abstract: A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.

公开(公告)号：US20210055756A1

公开(公告)日：2021-02-25

申请号：US16656524

申请日：2019-10-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G06F1/08 ,  H03L7/085 ,  H03K5/135

Abstract: A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.

公开(公告)号：US20210027820A1

公开(公告)日：2021-01-28

申请号：US16565407

申请日：2019-09-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.

公开(公告)号：US20180233191A1

公开(公告)日：2018-08-16

申请号：US15955701

申请日：2018-04-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C11/4093 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F12/00 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US09659618B1

公开(公告)日：2017-05-23

申请号：US15220403

申请日：2016-07-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  H03K19/00 ,  G06F3/06

CPC classification number: G11C7/222 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1689 ,  G11C7/1066 ,  G11C27/02 ,  H03K19/0005

Abstract: A memory interface, a memory control circuit unit, a memory storage device and a clock generation method are provided. The method includes: receiving a first data strobe signal and a second data strobe signal from a volatile memory, where the first data strobe signal and the second data strobe signal are differential signals corresponding to each other; if a relative relation between a first voltage value of the first data strobe signal and a reference voltage value of a reference voltage signal conforms to a default condition, generating a clock signal in response to the first data strobe signal and the second data strobe signal; and sampling a data signal from the volatile memory based on a raising edge and a falling edge of the clock signal. Thereby, an accuracy for sampling the data signal from the volatile memory can be improved.