公开(公告)号：US20170365328A1

公开(公告)日：2017-12-21

申请号：US15591114

申请日：2017-05-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US10304521B2

公开(公告)日：2019-05-28

申请号：US15955701

申请日：2018-04-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C5/14 ,  G11C11/4093 ,  G11C11/4099 ,  G11C11/4096 ,  G11C11/4074 ,  G06F13/16 ,  G11C7/10 ,  G11C11/00 ,  G06F12/00

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US09990983B2

公开(公告)日：2018-06-05

申请号：US15591114

申请日：2017-05-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C16/30 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US11977745B2

公开(公告)日：2024-05-07

申请号：US17886416

申请日：2022-08-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Hui Tseng ,  Chia-Lung Ma ,  Zhen-Yu Weng

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.

公开(公告)号：US20240020021A1

公开(公告)日：2024-01-18

申请号：US17886416

申请日：2022-08-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Hui Tseng ,  Chia-Lung Ma ,  Zhen-Yu Weng

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.

公开(公告)号：US20180233191A1

公开(公告)日：2018-08-16

申请号：US15955701

申请日：2018-04-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C11/4093 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F12/00 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.