公开(公告)号：US11797222B2

公开(公告)日：2023-10-24

申请号：US17577012

申请日：2022-01-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Po-Cheng Su ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.