公开(公告)号：US12008262B2

公开(公告)日：2024-06-11

申请号：US17080854

申请日：2020-10-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.

公开(公告)号：US11829644B2

公开(公告)日：2023-11-28

申请号：US17581858

申请日：2022-01-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Cheng Su ,  Chih-Wei Wang ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.

公开(公告)号：US20230176783A1

公开(公告)日：2023-06-08

申请号：US17581858

申请日：2022-01-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Cheng Su ,  Chih-Wei Wang ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.

公开(公告)号：US11797222B2

公开(公告)日：2023-10-24

申请号：US17577012

申请日：2022-01-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Po-Cheng Su ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.

公开(公告)号：US20230195361A1

公开(公告)日：2023-06-22

申请号：US17577012

申请日：2022-01-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Po-Cheng Su ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.

公开(公告)号：US20220107756A1

公开(公告)日：2022-04-07

申请号：US17080854

申请日：2020-10-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Chun-Wei Tsao ,  Chih-Wei Wang ,  Wei Lin

IPC: G06F3/06

Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.