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公开(公告)号：US12148486B2
公开(公告)日：2024-11-19
申请号：US18181546
申请日：2023-03-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsiao-Yi Lin , Shih-Jia Zeng , Chen Yang Tang , Shi-Chieh Hsu , Wei Lin
Abstract: A read voltage adjustment method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a write command sequence instructing to program a plurality of first memory cells in a rewritable non-volatile memory module; sending a first read command sequence instructing to read the programmed first memory cells using a first read voltage level to obtain first count information; obtaining first compensation information corresponding to the first read voltage level, wherein the first compensation information reflects a deviation in evenly programming the first memory cells to a plurality of states; and adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.
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公开(公告)号：US20240304235A1
公开(公告)日：2024-09-12
申请号：US18301275
申请日：2023-04-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Hao Chen , Po-Cheng Su , Shih-Jia Zeng , Yu-Cheng Hsu , Wei Lin
CPC classification number: G11C11/409 , G06F3/0679 , G11C16/26
Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.
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公开(公告)号：US11797222B2
公开(公告)日：2023-10-24
申请号：US17577012
申请日：2022-01-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Po-Cheng Su , Chih-Wei Wang , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
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4.发明公开公开(公告)号：US20230214150A1
公开(公告)日：2023-07-06
申请号：US17679109
申请日：2022-02-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chun-Wei Tsao , Hsiao-Yi Lin , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
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公开(公告)号：US12293784B2
公开(公告)日：2025-05-06
申请号：US18301275
申请日：2023-04-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Hao Chen , Po-Cheng Su , Shih-Jia Zeng , Yu-Cheng Hsu , Wei Lin
IPC: G11C7/00 , G06F3/06 , G11C11/409 , G11C16/26
Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.
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Patent Agency Ranking
公开(公告)号：US20240128987A1
公开(公告)日：2024-04-18
申请号：US17994399
申请日：2022-11-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Yi-Fang Chang , Chun-Wei Tsao , Chen-An Hsu , Wei Lin
CPC classification number: H03M13/1555 , H03M13/015 , H03M13/1575
Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
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公开(公告)号：US20220027089A1
公开(公告)日：2022-01-27
申请号：US16994668
申请日：2020-08-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Yu-Siang Yang , Szu-Wei Chen , Wei Lin
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.
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公开(公告)号：US20250078897A1
公开(公告)日：2025-03-06
申请号：US18481998
申请日：2023-10-05
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chen Yang Tang , Hsuan Ming Kuo , Shi-Chieh Hsu , Wei Lin
IPC: G11C11/406 , G11C29/52
Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.
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公开(公告)号：US20240265983A1
公开(公告)日：2024-08-08
申请号：US18181546
申请日：2023-03-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsiao-Yi Lin , Shih-Jia Zeng , Chen Yang Tang , Shi-Chieh Hsu , Wei Lin
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/3404
Abstract: A read voltage adjustment method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a write command sequence instructing to program a plurality of first memory cells in a rewritable non-volatile memory module; sending a first read command sequence instructing to read the programmed first memory cells using a first read voltage level to obtain first count information; obtaining first compensation information corresponding to the first read voltage level, wherein the first compensation information reflects a deviation in evenly programming the first memory cells to a plurality of states; and adjusting the first read voltage level according to the first count information, the first compensation information, and default count information corresponding to the first read voltage level.
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公开(公告)号：US12008262B2
公开(公告)日：2024-06-11
申请号：US17080854
申请日：2020-10-27
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chun-Wei Tsao , Chih-Wei Wang , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.
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