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    Programmable digital TDI EO/IR scanning focal plane array with multiple selectable TDI sub-banks
    12.
    发明授权
    Programmable digital TDI EO/IR scanning focal plane array with multiple selectable TDI sub-banks 有权

    公开(公告)号：US11463639B2

    公开(公告)日：2022-10-04

    申请号：US17091689

    申请日：2020-11-06

    Applicant: RAYTHEON COMPANY

    Inventor： Steven Botts ,  Bryan W. Kean ,  Richard J. Peralta ,  John L. Vampola ,  Micky R. Harris

    IPC: H04N5/369 ,  H04N5/33 ,  H04N5/359 ,  H04N5/372 ,  H04N5/378

    Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

    PROGRAMMABLE DIGITAL TDI EO/IR SCANNING FOCAL PLANE ARRAY WITH MULTIPLE SELECTABLE TDI SUB-BANKS
    13.
    发明申请
    PROGRAMMABLE DIGITAL TDI EO/IR SCANNING FOCAL PLANE ARRAY WITH MULTIPLE SELECTABLE TDI SUB-BANKS 审中-公开

    公开(公告)号：US20190373194A1

    公开(公告)日：2019-12-05

    申请号：US16426863

    申请日：2019-05-30

    Applicant: RAYTHEON COMPANY

    Inventor： Steven Botts ,  Bryan W. Kean ,  Richard J. Peralta ,  John L. Vampola ,  Micky R. Harris

    IPC: H04N5/369 ,  H04N5/33 ,  H04N5/378 ,  H04N5/372 ,  H04N5/359

    Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

    Extended high dynamic range direct injection circuit for imaging applications
    16.
    发明授权
    Extended high dynamic range direct injection circuit for imaging applications 有权

    公开(公告)号：US10063797B2

    公开(公告)日：2018-08-28

    申请号：US15388023

    申请日：2016-12-22

    Applicant: RAYTHEON COMPANY

    Inventor： John L. Vampola ,  Micky R. Harris ,  Bryan W. Kean ,  Steven Botts ,  Richard J. Peralta

    IPC: H04N5/355 ,  H04N5/378 ,  H04N5/374 ,  H04N5/353

    CPC classification number: H04N5/3559 ,  H04N5/3535 ,  H04N5/35527 ,  H04N5/3742 ,  H04N5/37452 ,  H04N5/378

    Abstract: According to one aspect, embodiments herein provide a unit cell circuit comprising a photodetector configured to generate a photo-current in response to receiving light, a first integration capacitor configured to accumulate charge corresponding to the photo-current, a second integration capacitor configured to accumulate charge corresponding to the photo-current, a charge diverting switch coupled to the photodetector and configured to selectively couple the first integration capacitor to the second integration capacitor and divert the photo-current to the second integration capacitor in response to a voltage across the first integration capacitor exceeding a threshold level, and read-out circuitry coupled to the first integration capacitor and the charge diverting switch and configured to read-out a first voltage sample from the first integration capacitor corresponding to charge accumulated on the first integration capacitor and to read-out a second voltage sample from the second integration capacitor corresponding to charge accumulated on the second integration capacitor.

    Single phase analog counter for a digital pixel
    17.
    发明授权
    Single phase analog counter for a digital pixel 有权

    公开(公告)号：US11456746B2

    公开(公告)日：2022-09-27

    申请号：US16749295

    申请日：2020-01-22

    Applicant: RAYTHEON COMPANY

    Inventor： Richard E. Wahl ,  Joshua J. Cantrell ,  John L. Vampola ,  Micky R. Harris

    IPC: H03K21/38 ,  G01J1/46 ,  H04N5/378 ,  G01J1/44 ,  H03M1/34

    Abstract: An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

    DIGITAL PIXEL HAVING HIGH SENSITIVITY AND DYNAMIC RANGE
    18.
    发明申请
    DIGITAL PIXEL HAVING HIGH SENSITIVITY AND DYNAMIC RANGE 有权

    公开(公告)号：US20210377470A1

    公开(公告)日：2021-12-02

    申请号：US16890483

    申请日：2020-06-02

    Applicant: Raytheon Company

    Inventor： Neil R. Malone ,  Micky Harris ,  Adam M. Kennedy ,  George Paloczi ,  John L. Vampola ,  Christian M. Boemler

    IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745

    Abstract: A digital pixel includes a capacitive transimpedence amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

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